The ADN4661BRZ-REEL7 is a quad LVDS line receiver from Analog Devices in SOIC-16, converting four LVDS (Low Voltage Differential Signaling) input pairs to four LVTTL outputs. LVDS uses a 350mV differential swing across 100-ohm termination, providing high noise immunity and low EMI at data rates up to 400Mbps. The receiver detects the differential voltage: when the non-inverting input (D+) is higher than the inverting input (D-) by more than 50mV, the output Y is LOW (LVTTL 0V); when D- is higher than D+, the output Y is HIGH (LVTTL 3.3V). The 50mV threshold provides 300mV noise margin from the 350mV signal swing. The internal 100-ohm termination resistor between each differential input pair eliminates the need for external termination, saving board space. The EN pin (active HIGH) enables all four outputs simultaneously; when disabled, outputs go to high-impedance state. Propagation delay is 1.5ns typical, critical for high-speed clock and data alignment. The device is pin-compatible with the SN65LVDS049 from TI.