MFRC52202HN1

The MFRC52202HN1 from NXP Semiconductors is the version 2.0 of the MFRC522 highly integrated reader/writer IC for contactless communication at 13.56 MHz, housed in a compact HVQFN-32 package (5 x 5 x 0.85 mm, SOT617-1). This device is one of the most widely used RFID reader ICs in the embedded systems community, supporting ISO/IEC 14443A/MIFARE and NTAG protocols for reading and writing contactless cards and transponders.

The MFRC52202HN1 integrates the complete analog front end (AFE), digital protocol processing, and host communication interfaces into a single chip. The internal transmitter provides buffered output drivers (TX1, TX2) that can directly drive a reader/writer antenna matched to 50 ohms with minimal external components. The receiver module includes a robust and efficient implementation for demodulating and decoding signals from ISO/IEC 14443A/MIFARE compatible cards, with a typical operating distance of up to 50 mm depending on antenna design and tuning.

The digital module manages the complete ISO/IEC 14443A framing and error detection (parity and CRC) functionality, along with MIFARE Classic authentication (CRYPTO1 encryption for MF1xxS20, MF1xxS50, MF1xxS70 in Read/Write mode). A 64-byte FIFO buffer facilitates efficient data transfer between the host and the contactless UART. The device supports three host communication interfaces: SPI (up to 10 Mbit/s), I2C (up to 400 kHz, 7-bit address programmable via EA pin and D1-D5), and serial UART (up to 1.2 Mbit/s), selectable by pin configuration.

Version 2.0 improvements over version 1.0 (MFRC52201HN1) include: increased stability in rough conditions, an additional timer prescaler for more flexible timing configurations, and corrected CRC handling when RX Multiple is set to 1. The MFRC52202HN1 is fully backward compatible with the MFRC52201HN1.

Power management features include a hardware power-down mode (via NRSTPD pin) with 5uA typical current consumption, and a software-controlled power-down mode with programmable timer for automatic wake-up. The device operates from a 2.5V to 3.6V supply, making it suitable for 3.3V microcontroller systems. The operating temperature range is -25C to 85C.

The HN1 suffix denotes HVQFN-32 package, and the ordering codes include ,151 and ,157 variants for different packaging options (tape and reel). The device is RoHS compliant, MSL Level 1, and classified as EAR99.

The MFRC52202HN1 operates as a 13.56 MHz RFID reader/writer, implementing the physical and data link layers of the ISO/IEC 14443A communication protocol between a host microcontroller and contactless cards or transponders.

Transmitter Operation: The internal transmitter generates the 13.56 MHz carrier frequency using an external 27.12 MHz crystal oscillator (connected to OSCIN/OSCOUT pins) with an internal PLL. The carrier is modulated using either 100% ASK (Type A modification) or various modulation depths as configured in the TxControlReg register. The modulated carrier is driven through two push-pull output stages (TX1 and TX2) that connect to the antenna via an LC matching network. When both TX1 and TX2 are enabled (TxControlReg bits 0 and 1 set), the outputs drive the antenna in push-pull configuration for maximum power delivery. The transmitter supports ISO/IEC 14443A transfer speeds: 106 kBd, 212 kBd, 424 kBd, and 848 kBd.

Receiver Operation: The receiver input (RX pin) captures the subcarrier signal from the card’s load modulation. The signal passes through a gain-controlled amplifier, then through I-channel and Q-channel demodulators using coherent detection with internally generated reference signals. The demodulated signals are digitized by an ADC and processed by the digital correlator for bit decoding. The receiver handles the complete ISO/IEC 14443A receive chain including bit-level framing, anti-collision protocol, and collision detection. The collision detection identifies bit positions where multiple cards transmit different values simultaneously.

Protocol Processing: The digital module (contactless UART) manages the complete ISO/IEC 14443A protocol stack: (1) REQA/WUPA command transmission for card activation, (2) Anti-collision sequence to select one card from multiple cards in the field, (3) SELECT command to confirm card selection, (4) MIFARE authentication (CRYPTO1 mutual authentication using secret key), (5) Read/Write operations with automatic CRC generation and verification. The 64-byte FIFO buffer stores transmitted and received data, allowing the host to read/write large data blocks without tight timing requirements.

Host Interface Selection: The interface mode is determined at power-up by the state of the I2C pin (pin 1) and the D1-D7 pins. When I2C pin is HIGH, the I2C interface is selected with the 7-bit slave address determined by the EA pin and D1-D5 pins. When I2C pin is LOW, either SPI or UART mode is selected based on pin configurations. In SPI mode, the device uses standard 4-wire SPI (NSS, SCK, MOSI, MISO) with NSS active-low chip select. In UART mode, the device uses serial communication with configurable baud rate.

MIFARE Authentication: The MFRC52202HN1 implements the CRYPTO1 stream cipher for MIFARE Classic authentication. During the authentication sequence, the reader sends an authentication command with the sector and key type (A or B), the card responds with a random number, and the reader and card perform a mutual three-pass authentication. After successful authentication, all subsequent read/write operations in that sector are encrypted using the CRYPTO1 cipher. The MFIN and MFOUT pins allow connection to a secure access module (SAM) for enhanced key management.

Interrupt System: The IRQ pin generates interrupts for various events including: timer expiration, end of transmit, receiver FIFO full/half-full/break, CRC error, and collision detection. The interrupt enable and status registers allow fine-grained control over which events trigger interrupts, enabling event-driven programming models that reduce host processor polling overhead.