STWD100NYWY3F

The STWD100NYWY3F from STMicroelectronics is a standalone hardware watchdog timer designed to monitor microcontroller operation and reset the system if the software fails to periodically service the watchdog. Unlike software-based watchdog implementations inside MCUs, the STWD100 is an independent hardware device that continues to function even if the MCU’s internal clock or software fails completely. The 3.3ms typical timeout period requires the MCU to toggle the WDI (Watchdog Input) pin at least every 3.3ms to prevent a watchdog reset; if the MCU fails to toggle WDI within the timeout window (1.7ms to 6.3ms over temperature and voltage), the WDO (Watchdog Output) pin goes low, signaling a fault condition. The WDO open-drain output can be connected directly to the MCU’s reset pin or to a power supervisor’s MR (Manual Reset) input. The edge-triggered WDI input accepts any logic transition (rising or falling edge) as a valid watchdog service pulse, making it compatible with any GPIO pin that can be toggled. The 7uA typical supply current is low enough for battery-powered applications. The EN (Enable) pin allows the watchdog to be disabled during system initialization or low-power sleep modes, preventing false watchdog resets during periods when the MCU is intentionally not servicing the watchdog. The extended -40 to +125C temperature range supports automotive and industrial applications. The STWD100 is pin-compatible with the TPS3823 watchdog timer from TI.

The STWD100NYWY3F operates as an independent hardware watchdog timer. Key subsystems include: (1) Internal Oscillator – a precision RC oscillator generates the timing reference for the watchdog timeout; the oscillator runs continuously when EN is high; the 3.3ms typical timeout is derived from this oscillator; the timeout varies from 1.7ms to 6.3ms over the full temperature and voltage range; (2) Watchdog Counter – a counter is clocked by the internal oscillator; when the counter reaches its terminal count (timeout), the WDO output is asserted low; each edge (rising or falling) on the WDI pin resets the counter to zero, restarting the timeout period; if WDI transitions occur before the counter reaches timeout, the watchdog never triggers; (3) WDO Output – an open-drain output that goes low when the watchdog timer expires (WDI not serviced within timeout); the open-drain configuration allows wired-OR connection with other reset sources (power supervisors, manual reset buttons); an external pull-up resistor (typically 10kOhm) is required; WDO remains low until WDI is serviced or EN is toggled; (4) EN Input – when EN is low, the watchdog is disabled (counter is held in reset, WDO is high-impedance); when EN goes high, the watchdog timer starts counting from zero; this allows the MCU to disable the watchdog during initialization or sleep; (5) Power-On Reset – an internal POR circuit keeps WDO low during power-up until VCC exceeds the POR threshold, ensuring a clean system reset on power application.

• Automotive ECU: STWD100 monitors MCU, WDO connects to system reset supervisor, MCU must toggle WDI every 3ms or ECU resets for safety
• Industrial PLC: hardware watchdog ensures PLC recovers from software hang, open-drain WDO wired-OR with power-fail reset
• Battery-powered sensor: 7uA current negligible in sleep budget, EN pin disables watchdog during deep sleep, re-enables on wake