74HC573PW

The 74HC573PW from Nexperia is an octal (8-bit) D-type transparent latch with 3-state outputs, housed in a 20-pin TSSOP package. It is one of the most widely used bus latch devices in digital system design, particularly for microprocessor and microcontroller address/data bus demultiplexing.

The 74HC573 is functionally identical to the 74HC373, but with a different pinout that places all data inputs on one side of the package and all outputs on the opposite side. This flow-through pinout dramatically simplifies PCB layout for bus-oriented designs, where the data bus flows from left to right (or top to bottom) through the latch. The 74HC373, by contrast, has inputs and outputs interleaved, making bus routing more complex.

The device provides two control functions: latch enable (LE) and output enable (OE). The LE pin controls whether the latches are transparent (passing input data to outputs) or holding (latching the last data). The OE pin controls whether the outputs are active (driving the bus) or in the high-impedance state (disconnected from the bus). These two controls operate independently: OE affects only the output buffers, not the internal latch state, so the latched data is preserved even when the outputs are disabled.

Transparent Latch Operation: When LE is HIGH, each D input passes directly through its respective latch to the corresponding Q output. The latch is said to be ‘transparent’ because the output follows the input with only the propagation delay (approximately 14ns at VCC=4.5V). This mode is used during the time when the microprocessor is driving the address/data bus with valid data. When LE transitions from HIGH to LOW, the data present at the D inputs at the moment of the falling edge is captured (latched) and held at the Q outputs. The latch then becomes opaque – changes on the D inputs no longer affect the Q outputs until LE goes HIGH again.

3-State Output Control: The OE pin controls the output buffers independently of the latch state. When OE is LOW (active), the outputs drive the bus with the latched data. When OE is HIGH, all outputs enter the high-impedance (Hi-Z) state, effectively disconnecting the device from the bus. This allows multiple devices to share a common output bus without contention. The internal latch continues to hold its data even when the outputs are disabled, so the data is immediately available when OE goes LOW again.

Microprocessor Bus Demultiplexing: The primary application of the 74HC573 is demultiplexing the combined address/data bus used by many microprocessors and microcontrollers. In these systems, the same physical pins carry both address and data information on different clock phases. The 74HC573 captures the address during the address phase (LE=HIGH, then LE goes LOW to latch), and the latched address remains stable on the outputs while the bus transitions to the data phase. This allows the system to use the address for memory decoding while the data bus is free for read/write operations.

The 74HC573 is also commonly used as an output port expander. A microcontroller writes data to the latch by driving the D inputs and pulsing LE. The latched data then drives external peripherals (LEDs, relays, displays) independently of the microcontroller bus state. The OE pin can be used to enable/disable the port outputs as needed.

The 74HC variant operates over the full 2.0V to 6.0V supply range with CMOS input levels, while the 74HCT variant operates at 4.5V to 5.5V with TTL-compatible input levels. The HCT variant is preferred when interfacing with 5V TTL or CMOS logic, while the HC variant is used for lower-voltage applications.

Input clamp diodes on all inputs allow interfacing with voltages in excess of VCC through current-limiting resistors. This feature is useful in mixed-voltage systems where input signals may come from a higher-voltage domain. The latch-up performance exceeds 100mA per JESD 78 Class II Level B, ensuring reliable operation in harsh electrical environments.

The 74HC573PW operates as 8 independent D-type transparent latches with common control inputs and 3-state output buffers.

Transparent Latch Cell: Each of the 8 latch cells consists of a data input (D), a transmission gate, a feedback inverter, and a buffer to the output. When LE is HIGH, the transmission gate connects the D input to the latch node, and the feedback inverter maintains the logic level. The output buffer drives the Q output with the value at the latch node. In this transparent state, the Q output follows the D input with a propagation delay determined by the transmission gate and output buffer delays (approximately 14ns at VCC=4.5V).

Latch Operation: When LE transitions from HIGH to LOW, the transmission gate opens, disconnecting the D input from the latch node. The feedback inverter then maintains the last logic level at the latch node indefinitely (as long as power is maintained). The Q output continues to drive the latched value. The critical timing parameter is the data setup time (tsu, typically 3-5ns): the D input must be stable for at least tsu before the falling edge of LE to ensure correct data capture. The data hold time (th) is typically 1-2ns after the LE falling edge.

3-State Output Buffer: Each output buffer consists of a pair of complementary MOSFETs (P-channel pull-up and N-channel pull-down) that can be enabled or disabled by the OE control. When OE is LOW (output enabled), the buffer operates normally, driving the output HIGH or LOW based on the latch data. When OE is HIGH (output disabled), both MOSFETs are turned off, placing the output in the high-impedance state. The output impedance in the Hi-Z state is typically >1Gohm, effectively disconnecting the device from the bus. The OE control does not affect the internal latch node – the latched data is preserved regardless of the OE state.

Control Independence: The LE and OE controls are completely independent. This means: (1) The latch can be updated (LE toggled) while the outputs are disabled (OE=HIGH), allowing the device to be pre-loaded with data before enabling the outputs. (2) The outputs can be disabled (OE=HIGH) while the latch retains its current data, allowing other devices to drive the bus. (3) Both controls can be operated simultaneously if desired, though care must be taken to meet the timing requirements for data capture.

Flow-Through Pinout: The TSSOP-20 package arranges the pins so that all data inputs (D0-D7) are on one side (pins 2-9) and all data outputs (Q0-Q7) are on the opposite side (pins 12-19). The control pins (OE at pin 1, LE at pin 11) and power pins (VCC at pin 20, GND at pin 10) are at the ends. This flow-through arrangement allows the device to be placed between two bus traces with minimal routing complexity – the input bus enters from one side, the output bus exits from the other side, and the control signals come from the ends.

CMOS Implementation: The device uses silicon-gate CMOS technology with complementary N-channel and P-channel MOSFETs. The CMOS implementation provides: (1) virtually zero static power dissipation (only leakage current flows when inputs are stable and the device is not switching); (2) rail-to-rail output swing (VOL near 0V, VOH near VCC); (3) symmetrical output drive capability (+/-7.8mA source and sink at VCC=4.5V); (4) high noise immunity due to the wide input thresholds (approximately 30-70% of VCC for HC variant).

Bus Contention Avoidance: When multiple 3-state devices share a common bus, only one device should drive the bus at any time. Bus contention occurs when two or more devices try to drive the bus to different logic levels simultaneously, which can cause excessive current flow and damage the output buffers. The system designer must ensure that the OE signals for all devices on the bus are mutually exclusive. A common technique is to use a decoder (such as the 74HC238) to generate the OE signals, ensuring that only one device is enabled at a time.