MCP4725A0T-E/CH

The MCP4725A0T-E/CH is a single-channel 12-bit voltage output Digital-to-Analog Converter (DAC) with integrated non-volatile EEPROM memory, manufactured by Microchip Technology in a 6-lead SOT-23 package. It uses a resistor-string architecture with an on-board precision output amplifier that enables rail-to-rail analog output swing from VSS to VDD. The DAC reference voltage is derived directly from VDD (2.7V to 5.5V), simplifying external component count. The 12-bit resolution provides 4,096 output levels with ±0.2 LSB typical DNL and ±2 LSB typical INL.

The integrated EEPROM stores the DAC register value and configuration bits, allowing the DAC output to be available immediately upon power-up without I2C communication from the host. The EEPROM write time is typically 25 ms, with an on-board charge pump generating the programming voltage. A Power-On Reset (POR) circuit ensures reliable startup.

The device supports eight possible I2C addresses. The A0 address bit is configurable via the external A0 pin (tied to VDD or VSS), while A2 and A1 bits are factory hard-wired. The MCP4725A0 variant has A2=0, A1=0, giving addresses 0x60 (A0=GND) and 0x61 (A0=VDD). The I2C interface supports Standard (100 kHz), Fast (400 kHz), and High-Speed (3.4 MHz) modes.

Power-down modes reduce supply current to 0.06 µA. Operating current is 210 µA (typical) in normal mode. Settling time is typically 6 µs. The device is AEC-Q100 Grade 1 qualified with an operating temperature range of -40°C to +125°C. MSL Level 1, RoHS compliant, EAR99. Tape and reel packaging, 3,000 units per reel. Microchip has marked the MCP4725 as Not Recommended for New Designs (NRND); consider MCP4726 for new designs.

The MCP4725A0T-E/CH operates as a 12-bit resistor-string DAC with I2C digital interface and non-volatile EEPROM storage.

Resistor-String DAC Architecture: The core uses a resistor-string (segmented resistor ladder) architecture where a 12-bit digital code selects one of 4,096 taps on a precision resistor divider between VDD and VSS. The selected tap voltage is buffered by an on-chip output amplifier to produce the analog output at VOUT. This architecture guarantees monotonicity — the output always increases (or stays the same) as the digital code increases. The output voltage is: VOUT = (D/4096) x VDD, where D is the 12-bit input code (0-4095) and VDD serves as both supply and reference.

Output Amplifier: The precision amplifier provides rail-to-rail output with 66-degree phase margin at 400 pF load. Output impedance is typically 1 ohm in normal mode. Short-circuit current is 15-24 mA. Slew rate is approximately 0.55 V/us, and settling time (1/4 to 3/4 scale) is typically 6 us.

EEPROM and Register Structure: The device contains a volatile DAC input register and non-volatile EEPROM. When the host writes a new DAC code via I2C, the value loads into the DAC register and immediately appears at the output. If the EEPROM write bit is set, the value is also programmed into EEPROM (25 ms typical write time). On power-up, the POR circuit automatically loads EEPROM contents into the DAC register. The EEPROM endurance is approximately 1 million write cycles with over 200 years data retention. An on-board charge pump generates the EEPROM programming voltage from VDD.

I2C Interface: The MCP4725 is an I2C slave only. The 7-bit address is: 1100 A2 A1 A0, where A2/A1 are factory programmed and A0 is set by the A0 pin. Write commands use Fast Mode (2 bytes) or Register Write (3 bytes). Read commands return DAC register and EEPROM contents. SDA and SCL are open-drain N-channel drivers requiring external pull-up resistors.

Power-Down Modes: Four modes available: Normal (DAC active) and three Power-Down modes differing in output amplifier termination resistance: 1 kohm, 100 kohm, or 500 kohm to VSS. These allow appropriate output load behavior when the DAC is inactive, useful for multi-DAC systems.