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GTL2014PW


4 位 LVTTL 至 GTL 收发器,3.0-3.6V,5V 容差输入,可调 Vref,DIR 引脚,TSSOP-14,-40~85°C

3000

有效库存
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制造商零件:

GTL2014PW

包装:

TSSOP-14 (SOT402-1)(5.0 x 4.4 x 1.1 毫米,0.65 毫米间距)

品牌:
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说明

NXP Semiconductors 的 GTL2014PW 是一款 4 位 LVTTL-to-GTL 转换收发器,采用 14 引脚 TSSOP 封装(5.0 x 4.4 mm)。它采用 3.0 V 至 3.6 V 单电源供电,典型供电电流为 4 mA。LVTTL A 端口输入具有 5.5 V 容差,GTL B 端口 I/O 工作电压高达 3.6 V,输出为开漏。方向引脚 (DIR) 可将器件配置为 GTL 至 LVTTL 采样接收器或 LVTTL 至 GTL 驱动器。VREF 在 0.5 V 至 VCC/2 之间可调,用于 GTL 门限参考。该器件支持部分掉电,并提供超过 2000 V HBM 的 ESD 保护。工作温度范围为 -40°C 至 +85°C。.

GTL2014PW 是恩智浦的一款 4 位转换收发器,设计用于将 3.3-V LVTTL 逻辑与处理器和内存控制器应用中常见的 GTL(Gunning Transceiver Logic)总线连接起来。该器件的引脚与 GTL2005 向后兼容,VREF 跟踪电压低至 0.5 V,适用于低压 CPU 接口。.

GTL 是一种开漏信号标准,使用基准电压 (VREF) 设置开关阈值。GTL 信号在 0 V(低电平)和终止电压 (VTT) 之间摆动,通常为 1.2 V 或 1.5 V,VREF 约为 VTT/2。与 LVTTL 相比,这种较低的电压摆幅可在高频率下实现更快的边沿速率和更低的功耗,从而使 GTL 成为处理器前端总线和高速存储器接口的首选。.

GTL2014 提供 4 位双向电平转换。当 DIR 为高电平时,器件从 LVTTL(A 端口)转换到 GTL(B 端口)--LVTTL 输入驱动 GTL 开漏输出。当 DIR 为低电平时,器件从 GTL(B 端口)转换到 LVTTL(A 端口)--GTL 输入根据 VREF 采样,结果显示在 LVTTL 输出上。.

A 端口 LVTTL 输入耐压高达 5.5 V,可直接连接 5 V CMOS 或 TTL 逻辑。B 端口 GTL 输入/输出为开漏,耐压高达 3.6 V,适用于标准 GTL(VTT = 1.2 V)和 GTL+ (VTT = 1.5 V)总线。VREF 引脚可接受 0.5 V 至 VCC/2 的基准电压(VCC = 3.6 V 时最大 1.8 V),适用于现代低压处理器。.

GTL2014 与 GTL2005 向后兼容,但两个器件的 A 端口和 B 端口标签互换。从 GTL2005 迁移过来的设计人员应注意这一引脚互换。GTL2014 改进了 0.8 V 以下的 VREF 线性度,传播延迟稍长,这是它与 GTL2005 的不同之处。.

**GTL 信号接口:** GTL 使用开漏驱动器,具有上拉至 VTT(通常为 1.2 V 或 1.5 V)的电阻。接收器将 GTL 总线电压与 VREF(约为 VTT/2)进行比较,以确定逻辑电平。当驱动器将总线拉至 VREF 以下时,接收器会检测到低电平。当驱动器释放时,上拉电阻将总线拉至 VREF 以上,接收器检测到高电平。.

**方向控制(DIR 引脚):** DIR 为高电平时,A 端口 LVTTL 输入驱动 B 端口 GTL 开漏输出。A 端口输入高电平会导致相应的 B 端口输出下拉(在 GTL 总线上断言为低电平);A 端口输入低电平会释放 B 端口输出(通过外部端接将 GTL 总线拉高)。当 DIR 为低电平时,B 端口 GTL 输入与 VREF 比较,结果驱动 A 端口 LVTTL 推挽输出。.

**VREF 参考电压:** VREF 引脚确定 GTL 接收器的开关阈值。它必须连接到干净的基准电压,通常通过电阻分压器从 VTT 导出。GTL2014 的 VREF 可精确跟踪至 0.5 V,支持低电压 CPU 内核。.

**部分掉电:** I/O 引脚设计用于在不使用 VCC 时承受电压,防止在热插拔和电源接续情况下出现回流电流损坏。.

针脚 名称 类型 说明
1 1A 输入/输出 LVTTL I/O 第 0 位;5.5V 容差输入;DIR=低时推挽输出(GTL 至 LVTTL)。
2 2A 输入/输出 LVTTL I/O 位 1;特性与 1A 相同
3 3A 输入/输出 LVTTL I/O 位 2
4 4A 输入/输出 LVTTL I/O 位 3
5 DIR I 方向控制;高电平 = LVTTL 至 GTL(A 驱动 B);低电平 = GTL 至 LVTTL(B 驱动 A);总线激活时不变
6 接地 G 地面
7 VREF I GTL 基准电压输入;0.5V 至 VCC/2;设置接收器阈值;连接至源自 VTT 的干净基准电压
8 1B 输入/输出 GTL I/O 第 0 位;开漏输出;3.6V 容差;接收时与 VREF 比较
9 2B 输入/输出 GTL I/O 位 1
10 3B 输入/输出 GTL I/O 位 2
11 4B 输入/输出 GTL I/O 位 3
12-14 GND/NC G/- 接地/无连接
应用 说明
处理器前端总线接口 将 3.3V LVTTL 芯片组逻辑连接至 GTL/GTL+ 处理器总线;DIR 引脚由芯片组控制;VREF 设置为 VTT/2(GTL+ 为 0.65V);4 位覆盖地址/数据线;使用多个设备实现更宽的总线
内存控制器 GTL 总线 在 3.3V 内存控制器和 GTL 端接的 DRAM 总线之间转换;开漏 B 端口驱动 GTL 端接电阻器;VREF 源自 VTT 电源;方向引脚在读写周期之间切换
模型 制造商 兼容性 主要区别
GTL2005PW 恩智浦 遗产前身 4 位 LVTTL 至 GTL 收发器;相同的 TSSOP-14 基底面;A/B 端口标签与 GTL2014 互换;VREF 低于 0.8V;传播延迟更短;仅用于传统的无须改造的替代品
GTL2010PW 恩智浦 系列变体(2 位) 2 位 LVTTL 至 GTL 收发器;较小的 TSSOP-8 封装;相同的电气特性;用于较窄的 GTL 总线
SN74GTL2014PWR TI 功能等效 4 位 LVTTL 至 GTL 收发器;TSSOP-14;规格相似;TI 提供的替代品;替代前请验证引脚输出的兼容性
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