TPS51362RVER

The TPS51362RVER is a 10-A integrated-FET synchronous buck converter from Texas Instruments, designed for point-of-load (POL) applications in notebook computers and embedded systems. It operates from a 3-V to 22-V input and produces an adjustable output from 0.6 V to 2.0 V, covering DDR memory VDDQ (1.35 V), VCCIO (1.05 V, 1.2 V), and core logic rails.

The D-CAP2 control topology is the key differentiator. Unlike traditional current-mode or voltage-mode control, D-CAP2 uses adaptive on-time control with internal ripple injection, eliminating the need for Type-II/III compensation components. This simplifies design and supports both POSCAP and all-MLCC output capacitor configurations without stability concerns — a critical advantage in compact designs where MLCCs are preferred for height and reliability.

The ULQ (Ultra-Low Quiescent) mode reduces the bias current to 100 µA when the LP# pin is pulled low, enabling long battery life during system standby. This is a significant improvement over standard auto-skip modes that typically draw 500 µA to 1 mA. In normal PWM mode, the device operates at a fixed 800-kHz frequency, balancing efficiency and inductor size.

The output voltage can be set by pin-strapping REFIN and REFIN2 pins (1.05 V, 1.2 V, 1.35 V, 1.5 V fixed options) without external resistors, or by a resistor divider from the 2.0-V VREF pin for any voltage from 0.6 V to 2.0 V. This flexibility supports multiple DDR generations and rail voltages with a single BOM.

The integrated bootstrap MOSFET switch eliminates the need for an external bootstrap diode. The low-side MOSFET RDS(on) sensing provides temperature-compensated overcurrent protection without an external sense resistor. The VQFN-CLIP-28 package achieves a compact 15.75-mm² footprint with an exposed thermal pad for efficient heat dissipation.

**D-CAP2 Control:** The TPS51362 uses TI’s D-CAP2 (Direct Capacitor-Area-Free 2nd generation) control, which combines adaptive on-time modulation with internal ripple injection. The error amplifier compares FB against an internal reference; the on-time generator produces a fixed-duration pulse (proportional to VIN/VOUT) each switching cycle. Internal ripple injection at FB emulates the inductor current ripple, providing the information needed for stable operation without external compensation. This topology is inherently stable with any output capacitor type (POSCAP, MLCC, or mixed) as long as ESR is above a minimum threshold.

**ULQ Mode:** When LP# is pulled low, the device enters ultra-low-quiescent mode. The controller reduces internal bias currents and switches to a pulse-skip mode where the switching frequency scales with load. At zero load, only 100 µA is drawn from the input supply. The output voltage regulation accuracy degrades slightly in ULQ mode but remains within DDR specification limits.

**Power Stage:** The integrated high-side and low-side MOSFETs are optimized for low duty-cycle operation (3-5 V output from 12-19 V input). The low-side RDS(on) is also used for current sensing — the voltage across the low-side FET during the off-time is measured and temperature-compensated to set the overcurrent limit threshold, eliminating an external sense resistor.

**Bootstrap and Pre-Bias:** The integrated bootstrap switch charges the BOOT capacitor from VDD through an internal MOSFET (not a diode), reducing the BOOT voltage drop and enabling start-up into pre-biased outputs without discharging the load first.