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SN74LS86N

Quad 2-input XOR gate, LS TTL, 14ns, PDIP-14

4000

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制造商零件：

SN74LS86N

包装：

PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

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说明

产品概览

The SN74LS86N from Texas Instruments contains four independent 2-input Exclusive-OR (XOR) gates — the TTL standard for parity, comparison, and arithmetic logic in a 14-pin PDIP package.

主要规格

Number of Gates 4 (quad 2-input XOR)
逻辑家族 LS (Low-power Schottky)
电源电压 4.75V to 5.25V
传播延迟 14ns typical (‘LS86A)
Output Drive IOL = 8mA, IOH = -0.4mA
功率耗散 30.5mW typical per device
工作温度 0°C to +70°C
包装 PDIP-14 (19.3 x 6.35mm)

特点

  • Quad 2-input XOR gates
  • Y = A ⊕ B = ĀB + AB̄
  • True/complement element: one input controls polarity
  • 14ns propagation delay (LS86A version)
  • Diode-clamped inputs

应用

  • Parity generators and checkers
  • Binary adders/subtractors
  • Logical comparators
  • True/complement signal control

The SN74LS86N from Texas Instruments contains four independent 2-input Exclusive-OR (XOR) gates. Each gate implements Y = A ⊕ B; the output is HIGH when exactly one input is HIGH, and LOW when both inputs are the same. The 7486 is the TTL equivalent of the CMOS CD4030/CD4070, with faster propagation delay (14ns vs 65ns) but limited to 5V supply. The XOR gate’s unique property — output HIGH when inputs differ — makes it indispensable for parity generation, binary addition (Sum = A⊕B), and comparison (A⊕B = 0 if A=B). As a true/complement element: with one input as control, the gate passes data when control=LOW or inverts data when control=HIGH. The LS86A suffix denotes the improved low-power Schottky version with better specs than the original 7486. The N suffix denotes the PDIP-14 through-hole package.

Each XOR gate in the SN74LS86N performs Y = A ⊕ B = ĀB + AB̄. Truth table: A=0,B=0 → Y=0; A=0,B=1 → Y=1; A=1,B=0 → Y=1; A=1,B=1 → Y=0. The output is HIGH when inputs are different (odd parity). As a true/complement element: B=0 → Y=A (pass through); B=1 → Y=Ā (invert). B controls whether A passes or inverts. For a 4-bit parity generator: 3 XOR gates cascaded: G1=A⊕B, G2=G1⊕C, G3=G2⊕D; G3 = A⊕B⊕C⊕D (1 if odd number of 1s). For a full adder: Sum = A⊕B⊕Cin, Cout = (A⊕B)·Cin + A·B; uses two XOR gates. For a controlled inverter: data on A, invert on B; Y = data when B=0, Y = NOT(data) when B=1; used in ALU design for complement operations.

针脚 名称 类型 说明
1 1A 输入 Gate 1 input A
2 1B 输入 Gate 1 input B
3 1Y 输出 Gate 1 output (A⊕B)
4 2A 输入 Gate 2 input A
5 2B 输入 Gate 2 input B
6 2Y 输出 Gate 2 output (A⊕B)
7 接地 电源 地面
8 3Y 输出 Gate 3 output (A⊕B)
9 3A 输入 Gate 3 input A
10 3B 输入 Gate 3 input B
11 4Y 输出 Gate 4 output (A⊕B)
12 4A 输入 Gate 4 input A
13 4B 输入 Gate 4 input B
14 VCC 电源 Supply (5V)
  • 4-Bit Parity Generator: 3 XOR gates cascaded; output = 1 for odd parity; used in serial communication error detection
  • Controlled Inverter: Data → A; invert control → B; Y = data (B=0) or NOT data (B=1); ALU complement operation
  • Full Adder: Two 7486 XOR gates + AND/OR gates; Sum = A⊕B⊕Cin; used in multi-bit adder chains
  • Comparator: A⊕B per bit; NOR all outputs; result = 1 if A=B, 0 if A≠B; 4-bit equality detector
模型 制造商 主要区别 包装 Supply
74LS86N TI/Nexperia Original TTL version with 5V-only supply, typical propagation delay 10-15ns DIP-14 5V TTL
74LS86D TI/Nexperia Surface-mount SOIC version of LS with identical logic function SOIC-14 5V TTL
74HC86D TI/Nexperia CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity SOIC-14 2-6V CMOS
74HC86N TI/Nexperia Through-hole DIP version of HC family for prototyping and repair DIP-14 2-6V CMOS
74HCT86D TI/Nexperia CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V SOIC-14 4.5-5.5V TTL-in
74HCT86N TI/Nexperia Through-hole DIP version of HCT family for prototyping and repair DIP-14 4.5-5.5V TTL-in
74AC86D TI/Nexperia Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC) SOIC-14 2-6V CMOS
74AC86N TI/Nexperia Through-hole DIP version of AC family for prototyping and repair DIP-14 2-6V CMOS
74LVC86D TI/Nexperia Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs SOIC-14 1.65-3.6V CMOS
74LVC86N TI/Nexperia Through-hole DIP version of LVC family for prototyping and repair DIP-14 1.65-3.6V CMOS

The 7486 is a Quad 2-Input Exclusive-OR Gate. Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.

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Tel / WhatsApp: +86 13760382860

服务与包装

Materialparts is a professional electronic component supplier based in Shenzhen, China, with over 20 years of global trading experience. We integrate component procurement, quality inspection, technical support, customized packaging, and global delivery services to provide one-stop supply chain solutions. Our business covers industrial control, automotive electronics, consumer electronics, medical devices and other industries. We always adhere to genuine sources, stable supply and considerate after-sales service.

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Address: Room 2919, Guoli Building, Huaqiang North, Futian District, Shenzhen, Guangdong, China
 

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