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SN74LS86N

Quad 2-input XOR gate, LS TTL, 14ns, PDIP-14

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Manufacturer Part：

SN74LS86N

Package：

PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

Brand：

Product Categories：

Integrated Circuits ICs, Interface ICs

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Description

Product Overview

The SN74LS86N from Texas Instruments contains four independent 2-input Exclusive-OR (XOR) gates — the TTL standard for parity, comparison, and arithmetic logic in a 14-pin PDIP package.

Key Specifications

Number of Gates	4 (quad 2-input XOR)
Logic Family	LS (Low-power Schottky)
Supply Voltage	4.75V to 5.25V
Propagation Delay	14ns typical (‘LS86A)
Output Drive	IOL = 8mA, IOH = -0.4mA
Power Dissipation	30.5mW typical per device
Operating Temperature	0°C to +70°C
Package	PDIP-14 (19.3 x 6.35mm)

Features

Quad 2-input XOR gates
Y = A ⊕ B = ĀB + AB̄
True/complement element: one input controls polarity
14ns propagation delay (LS86A version)
Diode-clamped inputs

Applications

Parity generators and checkers
Binary adders/subtractors
Logical comparators
True/complement signal control

Product Introduction:SN74LS86N Product Introduction

The SN74LS86N from Texas Instruments contains four independent 2-input Exclusive-OR (XOR) gates. Each gate implements Y = A ⊕ B; the output is HIGH when exactly one input is HIGH, and LOW when both inputs are the same. The 7486 is the TTL equivalent of the CMOS CD4030/CD4070, with faster propagation delay (14ns vs 65ns) but limited to 5V supply. The XOR gate’s unique property — output HIGH when inputs differ — makes it indispensable for parity generation, binary addition (Sum = A⊕B), and comparison (A⊕B = 0 if A=B). As a true/complement element: with one input as control, the gate passes data when control=LOW or inverts data when control=HIGH. The LS86A suffix denotes the improved low-power Schottky version with better specs than the original 7486. The N suffix denotes the PDIP-14 through-hole package.

Working Principle:SN74LS86N Working Principle

Each XOR gate in the SN74LS86N performs Y = A ⊕ B = ĀB + AB̄. Truth table: A=0,B=0 → Y=0; A=0,B=1 → Y=1; A=1,B=0 → Y=1; A=1,B=1 → Y=0. The output is HIGH when inputs are different (odd parity). As a true/complement element: B=0 → Y=A (pass through); B=1 → Y=Ā (invert). B controls whether A passes or inverts. For a 4-bit parity generator: 3 XOR gates cascaded: G1=A⊕B, G2=G1⊕C, G3=G2⊕D; G3 = A⊕B⊕C⊕D (1 if odd number of 1s). For a full adder: Sum = A⊕B⊕Cin, Cout = (A⊕B)·Cin + A·B; uses two XOR gates. For a controlled inverter: data on A, invert on B; Y = data when B=0, Y = NOT(data) when B=1; used in ALU design for complement operations.

Pin Description:SN74LS86N Pin Definition and Functions

Pin	Name	Type	Description
1	1A	Input	Gate 1 input A
2	1B	Input	Gate 1 input B
3	1Y	Output	Gate 1 output (A⊕B)
4	2A	Input	Gate 2 input A
5	2B	Input	Gate 2 input B
6	2Y	Output	Gate 2 output (A⊕B)
7	GND	Power	Ground
8	3Y	Output	Gate 3 output (A⊕B)
9	3A	Input	Gate 3 input A
10	3B	Input	Gate 3 input B
11	4Y	Output	Gate 4 output (A⊕B)
12	4A	Input	Gate 4 input A
13	4B	Input	Gate 4 input B
14	VCC	Power	Supply (5V)

Application Scenarios:In which products and applications isSN74LS86N used

4-Bit Parity Generator: 3 XOR gates cascaded; output = 1 for odd parity; used in serial communication error detection
Controlled Inverter: Data → A; invert control → B; Y = data (B=0) or NOT data (B=1); ALU complement operation
Full Adder: Two 7486 XOR gates + AND/OR gates; Sum = A⊕B⊕Cin; used in multi-bit adder chains
Comparator: A⊕B per bit; NOR all outputs; result = 1 if A=B, 0 if A≠B; 4-bit equality detector

Alternative Models:What chips are recommended as replacements for SN74LS86N

Model	Manufacturer	Key Difference	Package	Supply
74LS86N	TI/Nexperia	Original TTL version with 5V-only supply, typical propagation delay 10-15ns	DIP-14	5V TTL
74LS86D	TI/Nexperia	Surface-mount SOIC version of LS with identical logic function	SOIC-14	5V TTL
74HC86D	TI/Nexperia	CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity	SOIC-14	2-6V CMOS
74HC86N	TI/Nexperia	Through-hole DIP version of HC family for prototyping and repair	DIP-14	2-6V CMOS
74HCT86D	TI/Nexperia	CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V	SOIC-14	4.5-5.5V TTL-in
74HCT86N	TI/Nexperia	Through-hole DIP version of HCT family for prototyping and repair	DIP-14	4.5-5.5V TTL-in
74AC86D	TI/Nexperia	Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC)	SOIC-14	2-6V CMOS
74AC86N	TI/Nexperia	Through-hole DIP version of AC family for prototyping and repair	DIP-14	2-6V CMOS
74LVC86D	TI/Nexperia	Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs	SOIC-14	1.65-3.6V CMOS
74LVC86N	TI/Nexperia	Through-hole DIP version of LVC family for prototyping and repair	DIP-14	1.65-3.6V CMOS

The 7486 is a Quad 2-Input Exclusive-OR Gate. Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.