pic18f45k80-i/p

The PIC18F45K80-I/P from Microchip Technology is an 8-bit PIC18 microcontroller with an integrated CAN 2.0B controller (ECAN module) and eXtreme Low Power (XLP) technology, designed for cost-sensitive automotive, industrial, and building automation applications that require CAN bus connectivity with minimal power consumption.

The PIC18F45K80 belongs to the PIC18F66K80 family, which includes devices with 28 to 64 pins and 16 KB to 64 KB Flash. The PIC18F45K80 is the 40-pin, 32 KB Flash member. The -I/P suffix indicates industrial temperature range (-40 to +85 degrees C) in PDIP (plastic dual in-line) through-hole package, making it ideal for prototyping, hobbyist projects, and low-volume production where through-hole assembly is preferred.

The ECAN module is the primary differentiator of the PIC18F45K80. ECAN (Enhanced CAN) is Microchip’s implementation of the CAN 2.0B active specification, supporting both standard (11-bit) and extended (29-bit) message identifiers. The module includes 8 transmit/receive buffers (configurable as TX or RX), 16 acceptance filters with 16 masks for message filtering, and automatic bit timing calculation from the CAN bus baud rate. The ECAN module handles all CAN protocol layer functions (bit stuffing, CRC, error management, bit timing) in hardware, offloading the CPU for application tasks.

The 20 nA sleep current is remarkably low and is a hallmark of Microchip’s XLP technology. In applications where the MCU spends most of its time sleeping (e.g., waiting for a CAN message or a timer wake-up), the battery drain is dominated by the sleep current. At 20 nA, a 1000 mAh coin cell battery would last over 5700 years in sleep (theoretical), making the sleep current essentially zero for practical purposes. Even with the WDT running at 300 nA, the battery life is still measured in centuries.

The 1.8 V to 5.5 V operating voltage range is wider than typical PIC18 devices (which usually start at 2.0 V). The 1.8 V minimum enables operation from a single alkaline cell (1.5 V nominal, down to 0.9 V end-of-life with a boost converter) or from a single Li-Ion cell without regulation. The 5.5 V maximum allows direct connection to 5 V automotive and industrial systems.

The CTMU (Charge Time Measurement Unit) is a versatile peripheral that can be used for capacitive touch sensing (buttons, sliders, wheels), precision time measurement (resolution down to 1 ns), and capacitance-to-digital conversion. For touch sensing, the CTMU charges a sensor pad through a constant current source and measures the time to reach a threshold voltage. The measured time is proportional to the sensor capacitance, which changes when a finger is present. The CTMU enables touch user interfaces without external components.

The 11-channel 12-bit ADC provides higher resolution than the typical 10-bit ADC found on most PIC18 devices. The 12-bit resolution gives 4096 counts over the reference voltage range, providing 1.22 mV resolution at 5 V reference, compared to 4.88 mV for a 10-bit ADC. This improved resolution is valuable for sensor applications requiring higher precision.

The dual EUSART modules support LIN (Local Interconnect Network) bus communication in addition to standard UART. LIN is a single-wire, low-cost serial bus used in automotive sub-systems (door modules, seat controls, lighting). Each EUSART supports auto-baud detection, 9-bit addressing, and wake-on-start-bit for multi-node serial networks.

The PDIP-40 package is significant for several reasons: it is through-hole, making it easy to prototype on breadboards and through-hole PCBs; it is the same pinout as the classic PIC16F877A and PIC18F4520, enabling easy migration from these legacy devices; and it is one of the few CAN-equipped MCUs available in a through-hole package, making it accessible to hobbyists and educators who cannot solder surface-mount components.

Development is supported by Microchip’s MPLAB X IDE, MPLAB Code Configurator (MCC), and PICKit/ICD programmers. The PIC18F45K80 is also supported by the Microchip XC8 C compiler, which includes optimized libraries for ECAN, ADC, and communication peripherals.

The PIC18F45K80-I/P operates as an 8-bit Harvard architecture microcontroller with a 16-bit instruction word, integrating a CAN 2.0B protocol controller and advanced analog peripherals alongside the CPU core.

PIC18 Core: The PIC18 core uses a modified Harvard architecture with separate program and data memory buses. The program memory is organized as 16-bit words (not bytes), which allows most instructions to be encoded in a single word. The core executes most instructions in a single cycle (4 clock periods) at up to 64 MHz clock, giving 16 MIPS throughput. The instruction set includes 8×8 hardware multiply (single cycle), table read/write for Flash and EEPROM access, and conditional branch instructions. Unlike ARM Cortex-M cores, the PIC18 has no pipeline; each instruction is fetched and executed sequentially.

Memory Architecture: The 32 KB Flash is organized as 16K x 16-bit words. The data SRAM (3648 bytes) is accessed through the data bus using banked addressing (12 banks of 256 bytes each, plus Access RAM). The 1024-byte EEPROM is accessed through special registers (EEADR, EEDATA, EECON1, EECON2) and supports up to 1 million erase/write cycles. The Flash supports 10,000 erase/write cycles and 20-year data retention. Self-programming allows the application to write to its own Flash (for bootloaders and data logging) through the same table read/write mechanism.

ECAN Module: The Enhanced CAN module implements the CAN 2.0B active protocol in hardware. The module consists of a protocol engine, bit timing logic, and a message buffer system. The protocol engine handles frame formatting (start-of-frame, arbitration field, control field, data field, CRC field, ACK field, end-of-frame), bit stuffing/de-stuffing, error detection and signaling (bit error, stuff error, CRC error, form error, ACK error), error management (transmit/receive error counters, error passive/bus-off states), and bit timing (synchronization, propagation, phase segments).

The message buffer system uses 8 buffers that can be individually configured as transmit or receive buffers. Each buffer has dedicated registers for the message identifier (SID/EID), data length code (DLC), data bytes (up to 8), and status flags. The 16 acceptance filters and 16 masks allow the ECAN to accept or reject incoming messages based on the identifier field, reducing CPU interrupt load by filtering out irrelevant messages at the hardware level.

The ECAN supports bit rates from 10 kbps to 1 Mbps, determined by the CAN bus length and the oscillator frequency. The bit timing is configured through the BRGCONx registers, which set the baud rate prescaler, synchronization jump width, propagation segment, and phase segments 1 and 2. The module requires an external CAN transceiver (such as MCP2551 or SN65HVD230) to convert the MCU logic-level signals to the differential CAN bus levels.

CTMU: The Charge Time Measurement Unit consists of a precision constant current source, a discharge switch, and measurement circuitry. For capacitive touch sensing, the CTMU charges the sensor pad (connected to a GPIO pin configured as a capacitive input) with a constant current for a fixed time period, then the ADC measures the resulting voltage. When a finger is present, the additional capacitance causes the voltage to be lower (since V = I x T / C, higher C means lower V for constant I and T). The CTMU can also measure time intervals by charging a known capacitor with a constant current and measuring the voltage change, which gives the elapsed time with nanosecond-level resolution.

12-bit ADC: The ADC uses a successive approximation register (SAR) architecture with a capacitive charge redistribution DAC. The 12-bit resolution provides 4096 quantization levels. The ADC can be triggered by software, timer overflow, or external event. It supports automatic acquisition time calculation and can perform sequential scanning of multiple channels. The result is stored in 12-bit right-justified or left-justified format in the ADRESH:ADRESL register pair.

Power Management: The XLP technology achieves the ultra-low sleep current through several techniques: the on-chip voltage regulator is disabled in sleep mode (the core runs at 1.8 V internally, and the regulator is bypassed during sleep); the oscillator and all peripherals are stopped; only the WDT (if enabled) and the BOR (if enabled) remain active. The 20 nA sleep current assumes WDT and BOR are both disabled. With WDT enabled, the current increases to 300 nA. The MCU wakes from sleep on any enabled interrupt (external interrupt, CAN activity, EUSART start bit, timer overflow, etc.).

ICSP/ICD: The In-Circuit Serial Programming and In-Circuit Debug interface uses 2 pins (PGC, PGD) plus VDD, VSS, and MCLR. This allows Flash programming and real-time debugging (breakpoints, single-step, register view) without removing the device from the target board. The ICD interface is compatible with Microchip’s PICKit 3/4, ICD 3/4, and MPLAB Snap programmers/debuggers.