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CD4017BE

CMOS decade counter with 10 decoded outputs, 5.5MHz, 3-15V, 16-PDIP

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制造商零件：

CD4017BE

包装：

16-PDIP

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产品类别：

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说明

产品概览

The CD4017BE from Texas Instruments is a CMOS decade counter/divider with 10 decoded outputs that activate sequentially. Each clock pulse advances the active output by one position, enabling simple sequential control, LED chasers, and frequency division by 10. Packaged in 16-PDIP.

主要规格

逻辑家族	4000B Series CMOS
Outputs	10 decoded (Q0-Q9) + carry out
Clock Frequency	5.5MHz (typ at 10V)
电源电压	3V to 15V
Input Current	1uA (typ at 10V)
输出电流	1.5mA source, 3.6mA sink (at 10V)
包装	16-PDIP
工作温度	-55 to +125 C

特点

10 sequentially decoded outputs
Carry-out for cascading multiple devices
Clock enable input for gating
Master reset (active high) returns to Q0
Only one output active at a time
Wide supply voltage: 3V to 15V

应用

LED chaser and sequencer circuits
Frequency division by N (2-10)
Sequential timing and control
Counter and decoder applications

产品介绍：CD4017BE 产品介绍

The CD4017BE from Texas Instruments is a CMOS decade counter/divider with 10 decoded outputs that activate sequentially on each rising clock edge. The 5-stage Johnson counter internally generates 10 timing states, each decoded to one of the Q0-Q9 outputs. Only one output is high at any time, making it ideal for sequential control applications. The carry-out (CO) output produces a pulse every 10 clock cycles, enabling cascading for longer sequences. The clock enable input (active low) allows clock gating, and the master reset returns the counter to the Q0 state. With a wide 3V to 15V supply range and 5.5MHz maximum clock frequency, it is one of the most versatile logic ICs for hobbyist and educational projects.

工作原理：CD4017BE 工作原理

The CD4017BE uses a 5-stage Johnson counter (twisted-ring counter) as its core. A Johnson counter feeds back the complement of the last stage to the first stage input, creating a sequence of 2N states for N stages (10 states for 5 stages). The 10 states are decoded by AND gates to produce the Q0-Q9 outputs. On each rising edge of the CLOCK input, the counter advances by one state. When CLOCK ENABLE is high, clock pulses are ignored. When RESET goes high, all stages are cleared and Q0 becomes active. The CARRY OUT signal is derived from the first flip-flop output, producing one pulse per complete 10-count cycle. Cascading is achieved by connecting CO of the first stage to the CLOCK input of the next stage.

引脚说明：CD4017BE 引脚定义和功能

针脚	名称	功能
1	Q5	Decoded output 5
2	Q1	Decoded output 1
3	Q0	Decoded output 0 (active after reset)
4	Q2	Decoded output 2
5	Q6	Decoded output 6
6	Q7	Decoded output 7
7	Q3	Decoded output 3
8	VSS	地面
9	Q8	Decoded output 8
10	Q4	Decoded output 4
11	Q9	Decoded output 9
12	CO	Carry-out (1 pulse per 10 clocks)
13	CLK EN	Clock enable (active low)
14	CLK	Clock input (rising edge)
15	RST	Master reset (active high)
16	VDD	Supply voltage (3-15V)

Application Scenarios:In which products and applications isCD4017BE 中古

LED chaser circuits with 10 sequential outputs driven by NE555 clock
Frequency division by 2-10 by tapping the appropriate output
Sequential timing and control in industrial automation
Cascaded multi-digit counter displays using carry-out for chain connection

Alternative Models:What chips are recommended as replacements for CD4017BE

模型	制造商	主要区别
CD4022BE	TI	Octal counter (8 decoded outputs)
74HC4017	Nexperia	High-speed CMOS, 2-6V, 50MHz
74HC595	TI	Shift register with latch, more flexible
CD4060BE	TI	14-stage ripple counter with oscillator

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CD4017BE

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