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10M08SAM153I7G

MAX 10 FPGA, 8000 LEs, 153 I/O, 387Kbit RAM, on-chip Flash, 256-EQFP industrial

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Manufacturer Part：

10M08SAM153I7G

Package：

256-EQFP (22x22mm, 0.5mm pitch)

Description

Product Overview

The 10M08SAM153I7G from Intel is a MAX 10 FPGA with 8000 logic elements, 153 I/O pins, and 387Kbit embedded RAM in a 256-EQFP (22x22mm) package. With industrial-grade temperature range (-40°C to +100°C) and single 3.3V I/O supply, it provides instant-on CPLD-like functionality with FPGA density.

Key Specifications

Logic Elements	8000
LABs/CLBs	500
Total RAM	387,072 bits
I/O Pins	153
Core Voltage	1.2V
I/O Supply	2.85V – 3.465V
Speed Grade	-I7 (industrial)
Temperature Range	-40°C to +100°C
Package	256-EQFP (22x22mm)
MSL	3 (168 hours)

Features

Instant-on configuration from on-chip Flash — no external config device
8000 logic elements with dual-purpose I/O pins
387Kbit M9K embedded memory blocks
Single 3.3V I/O supply simplifies board design
Internal oscillator and ADC (10-bit, 1Msps) in select variants
In-system programming (JTAG) and dual-boot configuration support

Applications

CPLD replacement with higher density and on-chip Flash
Industrial control and I/O expansion
Bus bridging and protocol conversion
Motor control and power electronics logic

Product Introduction:10M08SAM153I7G Product Introduction

The 10M08SAM153I7G from Intel is a MAX 10 FPGA with 8000 logic elements and 153 I/O pins in a 256-EQFP (22x22mm) package. The MAX 10 family uniquely integrates configuration Flash on-chip, providing instant-on operation without external configuration devices — a key advantage over SRAM-based FPGAs. With 387Kbit of embedded M9K memory, industrial-grade temperature support (-40°C to +100°C), and single 3.3V I/O supply, it bridges the gap between CPLDs and FPGAs for applications requiring moderate logic density with instant-on reliability.

Working Principle:10M08SAM153I7G Working Principle

The 10M08SAM153I7G uses Intel’s MAX 10 architecture based on a 2D array of Logic Array Blocks (LABs), each containing 10 Logic Elements (LEs). Each LE consists of a 4-input look-up table (LUT), a programmable register, and carry/interconnect logic. The M9K embedded memory blocks can be configured as single-port or dual-port RAM, ROM, FIFO, or shift registers. The on-chip Flash stores the configuration bitstream, which is loaded into the SRAM configuration cells during power-up in approximately 10ms (instant-on). The dual-boot feature stores two configuration images, automatically falling back to the backup if the primary image is corrupted. JTAG interface supports in-system programming and boundary-scan testing.

Pin Description:10M08SAM153I7G Pin Definition and Functions

Pin Group	Count	Description
I/O Bank 1-8	153	General-purpose I/O (3.3V LVCMOS/LVTTL)
VCCIO	8	Per-bank I/O supply (2.85-3.465V)
VCCINT	4	Core voltage (1.2V, internal LDO)
VCCA	2	Analog supply (ADC, if available)
GND	16	Ground
TCK/TMS/TDI/TDO	4	JTAG programming interface
CONF_DONE/nCONFIG	2	Configuration control