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SN74LS86N

Quad 2-input XOR gate, LS TTL, 14ns, PDIP-14

5200

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制造商零件：

SN74LS86N

包装：

PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

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说明

产品概览

The SN74LS86N from Texas Instruments is a quad 2-input exclusive-OR (XOR) gate with LS TTL technology, 14ns propagation delay, and industry-standard 7486 pinout in a 14-pin PDIP package.

主要规格

Number of Gates 4 (quad 2-input XOR)
逻辑家族 LS (Low-power Schottky)
电源电压 4.75V to 5.25V (5V nominal)
传播延迟 14ns typical @ 5V
Output Drive (IOL/IOH) 8mA / -0.4mA
工作温度 0°C to +70°C
包装 PDIP-14 (19.3 x 6.35mm)

特点

  • Four independent 2-input XOR gates
  • LS TTL technology
  • 14ns typical propagation delay
  • Industry-standard 7486 pinout

应用

  • Parity generation and checking
  • Two’s complement subtraction (with adder)
  • Controlled inversion
  • Comparator circuits
  • Frequency doubling

The SN74LS86N from Texas Instruments contains four independent 2-input exclusive-OR (XOR) gates in a 14-pin PDIP package. Each gate performs the Boolean function Y = A XOR B; the output is HIGH when the inputs are different (01 or 10) and LOW when they are the same (00 or 11). The XOR gate is essential for arithmetic circuits: in an adder, XOR generates the sum bit; in a subtractor, XOR complements the subtrahend under control of a mode signal. When one input is used as a control, the XOR acts as a controlled inverter: if the control is HIGH, the data is inverted; if LOW, the data passes through unchanged. The XOR also serves as a 1-bit comparator: the output is HIGH when the two inputs differ. The N suffix denotes the PDIP-14 through-hole package.

Each XOR gate in the SN74LS86N performs Y = A XOR B = A ⊕ B. The truth table is: 00→0, 01→1, 10→1, 11→0. The output is HIGH when exactly one input is HIGH (exclusive OR). This is equivalent to Y = (A AND NOT-B) OR (NOT-A AND B), or more compactly Y = A ⊕ B. The XOR can also be expressed as Y = (A OR B) AND NOT(A AND B), which is OR minus AND. When input B is used as a control signal: if B=0, Y=A (data passes through); if B=1, Y=NOT-A (data is inverted). This controlled inversion is the basis for two’s complement subtraction: to compute A-B, set the control to 1 (complementing B) and feed the result into an adder with carry-in = 1. For parity generation, XOR all data bits together; the result is the parity bit. For parity checking, XOR all data bits plus the parity bit; if the result is 1, a parity error has occurred.

针脚 名称 类型 说明
1 1A 输入 Gate 1 input A
2 1B 输入 Gate 1 input B
3 1Y 输出 Gate 1 output (XOR)
4 2A 输入 Gate 2 input A
5 2B 输入 Gate 2 input B
6 2Y 输出 Gate 2 output (XOR)
7 接地 电源 地面
8 3Y 输出 Gate 3 output (XOR)
9 3A 输入 Gate 3 input A
10 3B 输入 Gate 3 input B
11 4Y 输出 Gate 4 output (XOR)
12 4A 输入 Gate 4 input A
13 4B 输入 Gate 4 input B
14 VCC 电源 Supply (4.75V to 5.25V)
  • Controlled Inverter: B input = SUB control; when B=1, output = NOT-A (invert for subtraction); when B=0, output = A (pass for addition)
  • Parity Generator: XOR all 8 data bits together; output is even parity bit; detect single-bit errors
  • Bit Comparator: XOR corresponding bits of two words; if all XOR outputs = 0, the words are equal
  • Frequency Doubler: Feed signal to one input, delayed version to other; output pulses on every edge
  • Adder Sum: XOR of A and B gives sum bit (without carry); pair with AND for carry = half adder
模型 制造商 主要区别 包装 Supply
74LS86N TI/Nexperia Original TTL version with 5V-only supply, typical propagation delay 10-15ns DIP-14 5V TTL
74LS86D TI/Nexperia Surface-mount SOIC version of LS with identical logic function SOIC-14 5V TTL
74HC86D TI/Nexperia CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity SOIC-14 2-6V CMOS
74HC86N TI/Nexperia Through-hole DIP version of HC family for prototyping and repair DIP-14 2-6V CMOS
74HCT86D TI/Nexperia CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V SOIC-14 4.5-5.5V TTL-in
74HCT86N TI/Nexperia Through-hole DIP version of HCT family for prototyping and repair DIP-14 4.5-5.5V TTL-in
74AC86D TI/Nexperia Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC) SOIC-14 2-6V CMOS
74AC86N TI/Nexperia Through-hole DIP version of AC family for prototyping and repair DIP-14 2-6V CMOS
74LVC86D TI/Nexperia Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs SOIC-14 1.65-3.6V CMOS
74LVC86N TI/Nexperia Through-hole DIP version of LVC family for prototyping and repair DIP-14 1.65-3.6V CMOS

The 7486 is a Quad 2-Input Exclusive-OR Gate. Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.

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Contact Information

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Tel / WhatsApp: +86 13760382860

服务与包装

Materialparts is a professional electronic component supplier based in Shenzhen, China, with over 20 years of global trading experience. We integrate component procurement, quality inspection, technical support, customized packaging, and global delivery services to provide one-stop supply chain solutions. Our business covers industrial control, automotive electronics, consumer electronics, medical devices and other industries. We always adhere to genuine sources, stable supply and considerate after-sales service.

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Contact Information

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Email: info@materialparts.com
Tel / WhatsApp: +86 13760382860
Address: Room 2919, Guoli Building, Huaqiang North, Futian District, Shenzhen, Guangdong, China
 

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