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SN74LS20N

Dual 4-input NAND gate, LS TTL, 15ns, PDIP-14

6000

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制造商零件：

SN74LS20N

包装：

PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

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说明

产品概览

The SN74LS20N from Texas Instruments contains two independent 4-input positive NAND gates in a 14-pin PDIP package — essential for implementing wide AND/NAND logic functions with minimal chip count.

主要规格

Number of Gates 2 (dual 4-input NAND)
逻辑家族 LS (Low-power Schottky)
电源电压 4.75V to 5.25V
传播延迟 15ns typical @ 5V
Output Drive (IOL/IOH) 8mA / -0.4mA
工作温度 0°C to +70°C
包装 PDIP-14 (19.3 x 6.35mm)

特点

  • Dual 4-input NAND gates
  • LS TTL technology
  • 15ns typical propagation delay
  • Industry-standard 7420 pinout

应用

  • 4-input AND function (NAND + inverter)
  • Address decoding with 4 conditions
  • Multi-condition gating
  • General-purpose logic

The SN74LS20N from Texas Instruments contains two independent 4-input NAND gates in a 14-pin PDIP package. Each gate performs Y = NOT(A AND B AND C AND D); the output is LOW only when ALL four inputs are HIGH. This 4-input NAND is valuable for address decoding and multi-condition gating where four signals must all be HIGH (or a combination of HIGH/LOW with inverters) to produce an active output. A 4-input AND function is obtained by adding an inverter after the NAND. Without the 7420, implementing a 4-input AND would require cascading two 2-input AND gates (7408) plus an extra gate — three gates versus one. DeMorgan’s theorem shows that a 4-input NAND is also equivalent to NOT-A OR NOT-B OR NOT-C OR NOT-D, making it useful for detecting when ANY input is LOW. The N suffix denotes the PDIP-14 through-hole package.

Each 4-input NAND gate performs Y = (A · B · C · D)’ — the output is LOW only when all four inputs A, B, C, and D are simultaneously HIGH. If any input is LOW, the output is HIGH. Truth table for one gate: 16 possible input combinations, only one (1111) produces LOW output. The NAND is a universal gate: any Boolean function can be implemented using only NAND gates. For a 4-input AND: Y = (A·B·C·D)” = A·B·C·D — add an inverter (7404 or one input of a NAND gate with tied inputs) after the 4-input NAND. For address decoding: if a memory device must be selected when A15=1, A14=1, A13=1, and MREQ=0, connect A15,A14,A13,MREQ’ (inverted) to the four inputs; the NAND output goes LOW only when all conditions are met (active-LOW chip select). The 15ns propagation delay means the output responds within 15ns of any input change.

针脚 名称 类型 说明
1 1A 输入 Gate 1 input A
2 1B 输入 Gate 1 input B
3 北卡罗来纳州 — 无连接
4 1C 输入 Gate 1 input C
5 1D 输入 Gate 1 input D
6 1Y 输出 Gate 1 output (NAND)
7 接地 电源 地面
8 2Y 输出 Gate 2 output (NAND)
9 2A 输入 Gate 2 input A
10 2B 输入 Gate 2 input B
11 北卡罗来纳州 — 无连接
12 2C 输入 Gate 2 input C
13 2D 输入 Gate 2 input D
14 VCC 电源 Supply (5V)

SN74LS20N uses the PDIP-14 package with standard 74LS TTL pinout: VCC at Pin 14, GND at Pin 7. Each NAND gate has four inputs and one output — Gate 1: Pins 1-4 (inputs), Pin 6 (output); Gate 2: Pins 9-12 (inputs), Pin 8 (output). Pins 5 and 13 are not connected. The LS technology provides typical propagation delay of 15ns and power dissipation of 2mW per gate. For push-pull active pull-up outputs, use SN74HC20N or SN74HCT20N which maintain the same pinout. The 74ALS20 provides lower power at similar speed as an advanced alternative.

  • 4-Input AND: 4 signals → 7420 NAND → 7404 inverter → active-HIGH when all 4 inputs are HIGH
  • Chip Select Decode: A15, A14, A13, MREQ’ → 7420 → active-LOW chip select; LOW only when all 4 are HIGH
  • Multi-Condition Enable: System OK = PowerGood AND NoFault AND NoOvertemp AND NoAlarm; 4 signals → NAND → inverter → active-HIGH system OK
  • 5+ Input AND: Combine 7420 output with 5th input in 7400 NAND → inverter; 5-input AND
模型 制造商 主要区别 包装 Supply
74LS20N TI/Nexperia Original TTL version with 5V-only supply, typical propagation delay 10-15ns DIP-14 5V TTL
74LS20D TI/Nexperia Surface-mount SOIC version of LS with identical logic function SOIC-14 5V TTL
74HC20D TI/Nexperia CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity SOIC-14 2-6V CMOS
74HC20N TI/Nexperia Through-hole DIP version of HC family for prototyping and repair DIP-14 2-6V CMOS
74HCT20D TI/Nexperia CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V SOIC-14 4.5-5.5V TTL-in
74HCT20N TI/Nexperia Through-hole DIP version of HCT family for prototyping and repair DIP-14 4.5-5.5V TTL-in
74AC20D TI/Nexperia Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC) SOIC-14 2-6V CMOS
74AC20N TI/Nexperia Through-hole DIP version of AC family for prototyping and repair DIP-14 2-6V CMOS
74LVC20D TI/Nexperia Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs SOIC-14 1.65-3.6V CMOS
74LVC20N TI/Nexperia Through-hole DIP version of LVC family for prototyping and repair DIP-14 1.65-3.6V CMOS

The 7420 is a Dual 4-Input NAND Gate. Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.

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Tel / WhatsApp: +86 13760382860

服务与包装

Materialparts is a professional electronic component supplier based in Shenzhen, China, with over 20 years of global trading experience. We integrate component procurement, quality inspection, technical support, customized packaging, and global delivery services to provide one-stop supply chain solutions. Our business covers industrial control, automotive electronics, consumer electronics, medical devices and other industries. We always adhere to genuine sources, stable supply and considerate after-sales service.

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Contact Information

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Address: Room 2919, Guoli Building, Huaqiang North, Futian District, Shenzhen, Guangdong, China
 

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