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SN74LS139N

Dual 2-to-4 decoder/demux, active-LOW, LS TTL, PDIP-16

5000

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制造商零件：

SN74LS139N

包装：

PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

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说明

产品概览

The SN74LS139N from Texas Instruments contains two independent 2-line to 4-line decoder/demultiplexers with active-LOW outputs and enable, ideal for address decoding and data demultiplexing in a 16-pin PDIP package.

主要规格

功能 Dual 2-line to 4-line decoder/demultiplexer
逻辑家族 LS (Low-power Schottky)
电源电压 4.75V to 5.25V
Select Inputs A, B per decoder
Enable G (active-LOW, per decoder)
Outputs Y0-Y3 (active-LOW, per decoder)
传播延迟 13–25ns typical
工作温度 0°C to +70°C
包装 PDIP-16 (19.3 x 6.35mm)

特点

  • Two independent 2-to-4 decoders in one package
  • Active-LOW enables and outputs
  • Can be used as demultiplexer (G = data input)
  • Cascadable for wider decoding

应用

  • Memory address decoding
  • I/O port decoding
  • Data demultiplexing
  • Chip select generation

The SN74LS139N from Texas Instruments contains two independent 2-line to 4-line decoders/demultiplexers. Each decoder has two select inputs (A, B) that determine which of the four active-LOW outputs (Y0-Y3) is driven LOW. The active-LOW enable (G) must be LOW for any output to be active; when G is HIGH, all outputs are HIGH regardless of select inputs. The 74139 is the workhorse of address decoding: with two address lines, it can generate four mutually exclusive active-LOW chip-select signals. Two 74139 decoders can be cascaded to create a 3-to-8 decoder (equivalent to 74138) using the enable of one decoder as the third select line. As a demultiplexer, the G input becomes the data input: the data on G is routed to the selected output (inverted), while unselected outputs remain HIGH. The N suffix denotes the PDIP-16 through-hole package.

Each decoder in the SN74LS139N implements the logic: when G=LOW, exactly one of Y0-Y3 is LOW based on the select inputs. When BA=00, Y0=LOW (all others HIGH); BA=01, Y1=LOW; BA=10, Y2=LOW; BA=11, Y3=LOW. When G=HIGH, all outputs are HIGH regardless of BA. The function: Yi = (G + (B’·A’ for i=0) + (B’·A for i=1) + (B·A’ for i=2) + (B·A for i=3))’. For a 3-to-8 decoder: connect A2 to 1G (decoder 1 enable) and through an inverter to 2G (decoder 2 enable); A0 and A1 connect to both decoders’ A and B inputs. When A2=LOW, decoder 1 is active (outputs 0-3); when A2=HIGH, decoder 2 is active (outputs 4-7). As a demultiplexer: serial data on G; A,B select the output; the selected output follows G (inverted), while unselected outputs stay HIGH. When G goes LOW, the selected output goes LOW; when G goes HIGH, all outputs go HIGH.

针脚 名称 类型 说明
1 1G 输入 Decoder 1 enable (active LOW)
2 1A 输入 Decoder 1 select A (LSB)
3 1B 输入 Decoder 1 select B (MSB)
4 1Y0 输出 Decoder 1 output 0 (active LOW)
5 1Y1 输出 Decoder 1 output 1 (active LOW)
6 1Y2 输出 Decoder 1 output 2 (active LOW)
7 1Y3 输出 Decoder 1 output 3 (active LOW)
8 接地 电源 地面
9 2Y3 输出 Decoder 2 output 3 (active LOW)
10 2Y2 输出 Decoder 2 output 2 (active LOW)
11 2Y1 输出 Decoder 2 output 1 (active LOW)
12 2Y0 输出 Decoder 2 output 0 (active LOW)
13 2B 输入 Decoder 2 select B (MSB)
14 2A 输入 Decoder 2 select A (LSB)
15 2G 输入 Decoder 2 enable (active LOW)
16 VCC 电源 Supply (5V)
  • Chip Select Generation: 2 address lines → A,B; G tied LOW; Y0-Y3 → chip selects for 4 peripheral ICs; one address decodes to one active-LOW CS
  • 3-to-8 Decoder: A2 → 1G (direct) and 2G (via inverter); A0,A1 → both decoders; 8 active-LOW outputs for memory chip selects
  • Demultiplexer: Serial data on G; A,B select output; data appears (inverted) on selected output; 1-to-4 data routing
  • I/O Port Decode: High address bits → 74139; Y0=IO port 0, Y1=IO port 1, etc.; combined with RD/WR for read/write strobes
模型 制造商 主要区别 包装 Supply
74LS139N TI/Nexperia Original TTL version with 5V-only supply, typical propagation delay 10-15ns DIP-16 5V TTL
74LS139D TI/Nexperia Surface-mount SOIC version of LS with identical logic function SOIC-16 5V TTL
74HC139D TI/Nexperia CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity SOIC-16 2-6V CMOS
74HC139N TI/Nexperia Through-hole DIP version of HC family for prototyping and repair DIP-16 2-6V CMOS
74HCT139D TI/Nexperia CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V SOIC-16 4.5-5.5V TTL-in
74HCT139N TI/Nexperia Through-hole DIP version of HCT family for prototyping and repair DIP-16 4.5-5.5V TTL-in
74LVC139D TI/Nexperia Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs SOIC-16 1.65-3.6V CMOS
74LVC139N TI/Nexperia Through-hole DIP version of LVC family for prototyping and repair DIP-16 1.65-3.6V CMOS

The 74139 is a Dual 2-Line to 4-Line Decoder/Demultiplexer. Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.

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