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SN74LS138N

3-to-8 decoder/demux, active-low outputs, 3 enables, PDIP-16

6000

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制造商零件：

SN74LS138N

包装：

PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

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说明

产品概览

The SN74LS138N from Texas Instruments is a 3-line to 8-line decoder/demultiplexer with three enable inputs (two active-low, one active-high) and active-low outputs in a 16-pin PDIP package.

主要规格

功能 3-line to 8-line decoder/demultiplexer
逻辑家族 LS (Low-power Schottky)
电源电压 4.75V to 5.25V (5V nominal)
Select Inputs 3 (A, B, C) — C is MSB
Outputs 8 (Y0-Y7, active-low)
Enable Inputs G1 (active-high), G2A and G2B (active-low)
传播延迟 22ns typical (select to output)
工作温度 0°C to +70°C
包装 PDIP-16 (19.3 x 6.35mm)

特点

  • 3-to-8 line decoder/demultiplexer
  • Active-low outputs for direct chip-select generation
  • Three enable inputs for cascading
  • 22ns typical propagation delay
  • Multiple 138s can be combined for larger decoding

应用

  • Memory address decoding
  • I/O port selection
  • Chip-select generation
  • Data demultiplexing
  • Cascaded larger decoders

The SN74LS138N from Texas Instruments is a 3-line to 8-line decoder/demultiplexer that takes a 3-bit binary address (A, B, C) and asserts one of eight active-low outputs (Y0-Y7). It is the most commonly used address decoder in digital systems, generating chip-select signals for memory and peripheral ICs. The three enable inputs—G1 (active-high) and G2A, G2B (both active-low)—must all be properly asserted for any output to be active; if any enable is inactive, all outputs remain HIGH (inactive). This enables cascading: a 4-to-16 decoder is built from two 138s by connecting the MSB address bit to G1 of one and G2A of the other. The 22ns propagation delay is fast enough for microprocessor address decoding in most 8-bit and 16-bit systems. The N suffix denotes the PDIP-16 through-hole package.

The SN74LS138N decodes a 3-bit binary input (CBA) to assert one of eight active-low outputs. For input CBA = 000, output Y0 goes LOW (all others remain HIGH). For CBA = 101, Y5 goes LOW, etc. The three enable inputs must all be asserted for the device to function: G1 must be HIGH, and both G2A and G2B must be LOW. If any enable is not satisfied, all eight outputs remain HIGH (inactive), regardless of the address inputs. For address decoding, the address lines connect to C, B, A, and the enables are used for higher-order address qualification. For example, in a 64K memory space with eight 8K devices: A0-A12 connect to each device’s address inputs, A13-A15 connect to the 138’s C, B, A inputs, and a master enable (e.g., MREQ) connects to G1. The 138 then selects one of eight devices based on A15-A13. For a 4-to-16 decoder using two 138s: A0-A2 go to both devices’ CBA inputs; A3 goes to G1 of the first and G2A of the second; the first device decodes addresses 0-7, the second decodes 8-15.

针脚 名称 类型 说明
1 A 输入 Address input A (LSB)
2 B 输入 Address input B
3 C 输入 Address input C (MSB)
4 G2A 输入 Enable (active-low)
5 G2B 输入 Enable (active-low)
6 G1 输入 Enable (active-high)
7 Y7 输出 Output 7 (active-low)
8 接地 电源 地面
9 Y6 输出 Output 6 (active-low)
10 Y5 输出 Output 5 (active-low)
11 Y4 输出 Output 4 (active-low)
12 Y3 输出 Output 3 (active-low)
13 Y2 输出 Output 2 (active-low)
14 Y1 输出 Output 1 (active-low)
15 Y0 输出 Output 0 (active-low)
16 VCC 电源 Supply (4.75V to 5.25V)

SN74LS138N uses the PDIP-16 package: VCC at Pin 16, GND at Pin 8. Three binary select inputs (A=Pin 1, B=Pin 2, C=Pin 3) decode to one of eight active-low outputs (Y0=Pin 15 through Y7=Pin 7). Three enable inputs control the device: G1=Pin 6 (active-high), G2A=Pin 4 (active-low), G2B=Pin 5 (active-low). All enables must be active for any output to go low. This 3-enable scheme allows cascading for 4-to-16 or 5-to-32 decoding without external logic. The active-low outputs interface directly with active-low TTL chip selects. For 2-to-4 decoding, use SN74LS139N (dual 2-to-4 decoder in the same DIP-16).

  • Memory Decode: A15-A13 → CBA; MREQ → G1; Y0-Y7 → /CS of 8 memory devices; each gets 8K address space
  • I/O Port Select: Low address bits → CBA; IORQ → G1; Y0-Y7 → /CS of 8 peripheral chips
  • 4-to-16 Decode: Two 138s; A3 selects which chip; A0-A2 selects output within chip; 16 active-low outputs
  • Demultiplexer: Data signal on G1; A0-A2 select which output gets the data; G2A=G2B=LOW
  • LED Scanner: Counter on CBA; Y0-Y7 drive LEDs (active-low = sink); sequentially lights 8 LEDs
模型 制造商 主要区别 包装 Supply
74LS138N TI/Nexperia Original TTL version with 5V-only supply, typical propagation delay 10-15ns DIP-16 5V TTL
74LS138D TI/Nexperia Surface-mount SOIC version of LS with identical logic function SOIC-16 5V TTL
74HC138D TI/Nexperia CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity SOIC-16 2-6V CMOS
74HC138N TI/Nexperia Through-hole DIP version of HC family for prototyping and repair DIP-16 2-6V CMOS
74HCT138D TI/Nexperia CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V SOIC-16 4.5-5.5V TTL-in
74HCT138N TI/Nexperia Through-hole DIP version of HCT family for prototyping and repair DIP-16 4.5-5.5V TTL-in
74AC138D TI/Nexperia Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC) SOIC-16 2-6V CMOS
74AC138N TI/Nexperia Through-hole DIP version of AC family for prototyping and repair DIP-16 2-6V CMOS
74LVC138D TI/Nexperia Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs SOIC-16 1.65-3.6V CMOS
74LVC138N TI/Nexperia Through-hole DIP version of LVC family for prototyping and repair DIP-16 1.65-3.6V CMOS

The 74138 is a 3-Line to 8-Line Decoder/Demultiplexer. Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.

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