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CD4025BE

Triple 3-input NOR gate, CMOS 3-18V, 60ns, PDIP-14

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制造商零件：

CD4025BE

包装：

PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

品牌：

产品类别：

集成电路 IC, 接口集成电路

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说明

产品概览

The CD4025BE from Texas Instruments contains three independent 3-input NOR gates in a 14-pin PDIP package — the CMOS complement of the CD4023 NAND, providing the direct NOR function across the 3V-18V supply range.

主要规格

Number of Gates	3 (triple 3-input NOR)
Technology	CD4000B CMOS
电源电压	3V to 18V
传播延迟	60ns typical @ VDD=10V
静态电流	0.01µA typical @ 25°C
工作温度	-55°C to +125°C
包装	PDIP-14 (19.3 x 6.35mm)

特点

Triple 3-input NOR gates
Wide supply voltage: 3V to 18V
Output HIGH only when ALL inputs are LOW
Near-zero quiescent current

应用

All-zero detection
Negative logic OR functions
Active-LOW signal combining
General CMOS logic

产品介绍：CD4025BE 产品介绍

The CD4025BE from Texas Instruments contains three independent 3-input NOR gates. Each gate implements Y = NOT(A OR B OR C); the output is HIGH only when all three inputs are LOW. The 3-input NOR is equivalent to a 3-input OR followed by an inverter, but implemented directly in a single gate stage for lower propagation delay. The NOR function is fundamental in digital logic: it is a universal gate (NOR alone can implement any Boolean function). For all-zero detection: three control lines into a NOR gate → output HIGH only when all three lines are LOW (inactive). For active-LOW combining: the NOR gate treats LOW inputs as ‘active’; any one active-LOW input drives the output HIGH. By DeMorgan’s theorem, the NOR function is also the AND of complemented inputs: Y = A’·B’·C’. This means a 3-input NOR can detect when all three inputs are simultaneously LOW — useful for monitoring multiple fault lines or status signals. The BE suffix denotes the PDIP-14 package.

工作原理：CD4025BE 工作原理

Each NOR gate in the CD4025BE performs Y = (A + B + C)’ = NOT(A OR B OR C). The output is HIGH only when ALL inputs A, B, and C are LOW. If ANY input is HIGH, the output is LOW. For a 3-input NOR: (0,0,0)→1; (0,0,1)→0; (0,1,0)→0; (0,1,1)→0; (1,0,0)→0; (1,0,1)→0; (1,1,0)→0; (1,1,1)→0. Only 1 of 8 input combinations produces a HIGH output. By DeMorgan’s theorem: Y = A’·B’·C’ (AND of complements). This means the 3-input NOR is an all-zero detector: the output goes HIGH only when every input is zero. For active-LOW logic (where LOW = active): the NOR gate acts as an OR of active signals — any active input produces an active-HIGH output. Unused inputs should be tied to VDD or VSS (not left floating) to prevent erratic output behavior from CMOS input noise sensitivity.

引脚说明：CD4025BE 引脚定义和功能

针脚	名称	类型	说明
1	1A	输入	Gate 1 input A
2	1B	输入	Gate 1 input B
3	2A	输入	Gate 2 input A
4	2B	输入	Gate 2 input B
5	2C	输入	Gate 2 input C
6	2Y	输出	Gate 2 output
7	VSS	电源	地面
8	3Y	输出	Gate 3 output
9	3A	输入	Gate 3 input A
10	3B	输入	Gate 3 input B
11	3C	输入	Gate 3 input C
12	1Y	输出	Gate 1 output
13	1C	输入	Gate 1 input C
14	VDD	电源	Supply (3V to 18V)

Application Scenarios:In which products and applications isCD4025BE 中古

All-Zero Detection: Three status signals → A,B,C; Y=HIGH only when all three are LOW; idle detector or no-fault indicator
Active-LOW OR: Three active-LOW interrupt lines → NOR gate; Y=HIGH when any interrupt is active (LOW); single active-HIGH interrupt request
Combinational Logic: NOR is universal; combine with other gates for any Boolean function of 3 variables
SR Latch: Two 3-input NOR gates cross-coupled; 2 inputs for Set/Reset; remaining inputs for additional control or tied LOW

Alternative Models:What chips are recommended as replacements for CD4025BE

模型	制造商	主要区别	包装	Supply
CD4025BM	TI	SOIC-14 surface-mount version with identical logic function and 3-18V range	SOIC-14	3-18V
CD4025BE	TI	Through-hole DIP version for prototyping and legacy board repair	DIP-14	3-18V
HEF4025BT	恩智浦	Pin-compatible CMOS version with improved ESD protection and 3-15V supply	SOIC-14	3-15V
MC144025BDR2G	onsemi	Pin-compatible equivalent with RoHS compliance and AEC-Q100 automotive option	SOIC-14	3-18V
74HC27D	TI/Nexperia	HC CMOS version with higher speed and 2-6V supply for modern logic systems	SOIC-14	2-6V
74HC27N	TI/Nexperia	HC CMOS through-hole version for prototyping with 2-6V supply range	DIP-14	2-6V
74HCT27D	Nexperia	HCT version with TTL-compatible inputs for mixed 5V TTL/CMOS systems	SOIC-14	4.5-5.5V

CD4025 is the CMOS 4000-series triple 3-input nor gate operating over the wide 3-18V supply range. The HEF4025 (NXP) and MC144025 (onsemi) are direct pin-compatible equivalents. For higher speed at the cost of narrower voltage range, the 74HC27 HC/HCT families offer significantly faster propagation delay and lower power consumption at 2-6V. Surface-mount versions use the BM/M suffix (SOIC); through-hole versions use the BE suffix (DIP).

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