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TPS3808G09DBVR

0.84V supervisor, 2.4uA Iq, prog delay 1.25ms-10s, SOT-23-6

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Manufacturer Part：

TPS3808G09DBVR

Package：

SOT-23-6 (2.9 x 1.6 x 1.15 mm)

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Description

Product Overview

The TPS3808G09DBVR from Texas Instruments is an ultra-low quiescent current microprocessor supervisor with programmable delay in a 6-pin SOT-23 package. With 0.84V fixed threshold (for 0.9V rail monitoring), 0.5% threshold accuracy, 2.4uA typical Iq, and adjustable reset delay from 1.25ms to 10s, it is ideal for battery-powered systems monitoring low-voltage core rails.

Key Specifications

Threshold Voltage 0.84V nominal (for 0.9V rail)
Threshold Accuracy 0.5% typical (for VIT <= 3.3V)
Supply Voltage 1.7V to 6.5V
Quiescent Current 2.4 uA typical
Reset Delay 1.25ms to 10s (programmable via CT pin)
CT Pin Options Open = 20ms; R to VDD = 300ms; C to GND = adjustable
Manual Reset (MR) Yes (active low)
RESET Output Open-drain, active low
Operating Temperature -40 to +125 C
Package SOT-23-6 (2.9 x 1.6 mm)
Status Active

Features

  • Ultra-low 2.4uA quiescent current
  • 0.5% threshold accuracy
  • 0.84V fixed threshold for 0.9V core monitoring
  • Programmable reset delay: 1.25ms to 10s
  • Three CT pin options: 20ms, 300ms, or custom
  • Manual reset input
  • Open-drain RESET output
  • -40 to 125C operating range

Applications

  • DSP and microcontroller core voltage monitoring
  • Battery-powered portable devices
  • FPGA and ASIC applications
  • Low-voltage rail supervision

The TPS3808G09DBVR from Texas Instruments is an ultra-low quiescent current programmable-delay supervisory circuit in a 6-pin SOT-23 package. The G09 denotes a fixed threshold voltage of 0.84V (designed for monitoring a 0.9V core rail), DBV denotes SOT-23-6 package, and R denotes tape and reel (3000 pcs/reel). The device monitors the SENSE pin voltage and asserts the open-drain RESET output when it drops below 0.84V, or when the manual reset (MR) pin is pulled low. The 0.5% threshold accuracy for voltages up to 3.3V is achieved through an internal precision bandgap reference. The reset delay is highly flexible: leaving CT pin open sets 20ms, connecting CT to VDD via a resistor sets 300ms, or connecting CT to an external capacitor allows adjustment from 1.25ms to 10s. The 2.4uA typical quiescent current makes this device exceptionally well-suited for battery-powered applications where supply current must be minimized.

The TPS3808G09DBVR operates through three subsystems: (1) Voltage Monitoring: A precision comparator monitors the SENSE pin against the internal 0.84V reference. The bandgap reference is temperature-compensated to achieve 0.5% accuracy. When SENSE drops below the threshold (VIT- = 0.84V – hysteresis), RESET asserts. When SENSE rises above VIT+, the reset timer starts. (2) Reset Timer: The CT pin controls the reset delay. With CT open, an internal 20ms timer is used. Connecting CT to VDD through a resistor (typically 200kOhm) selects a 300ms delay. For custom delays, an external capacitor on CT sets the delay: td = CT(nF) x 5.5 (ms/nF), ranging from 1.25ms (no capacitor) to 10s (with a large capacitor). The timer ensures the supervised processor has adequate time for power-on initialization before RESET de-asserts. (3) Manual Reset: The MR pin allows external reset triggering (active low). MR has an internal pullup and can be driven by a push-button, watchdog output, or another supervisor. MR and SENSE are logically ORed: either condition causes RESET assertion.

Pin Name Type Description
1 RESET Output Open-drain reset output (active low)
2 GND Power Ground
3 MR Input Manual reset (active low, internal pullup)
4 CT I/O Delay control (open=20ms, R to VDD=300ms, C to GND=custom)
5 VDD Power Supply voltage (1.7-6.5V)
6 SENSE Input Voltage sense input (0.84V threshold)
  • FPGA core voltage monitoring at 0.9V with 0.84V threshold and 300ms reset delay (CT pin with resistor to VDD)
  • Battery-powered MCU with 2.4uA supervisor Iq, monitoring 0.9V LDO output with custom 500ms delay via CT capacitor
  • ASIC power-on reset for 0.9V core rail with manual reset push-button on MR pin and 20ms delay (CT open)
  • Multi-rail system with TPS3808G09 monitoring 0.9V core and another TPS3808 variant monitoring 1.8V I/O
Model Manufacturer Threshold Iq Notes
TPS3808G12DBVR TI 1.08V 2.4uA For 1.2V rail
TPS3808G33DBVR TI 2.93V 2.4uA For 3.3V rail
TPS3808G01DBVR TI Adjustable 2.4uA SENSE pin adjustable down to 0.4V
TPS3839K33DBVR TI 2.93V 150nA Nano-power, no MR/CT
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