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SN74LVC1G86DCKR

Single 2-input XOR gate, 1.65-5.5V, 4ns tpd, ±24mA, OVT inputs, controlled inversion, SC70-5

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Manufacturer Part：

SN74LVC1G86DCKR

Package：

SC70-5 / SOT-353 (2.0 x 1.25 x 1.0mm)

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Description

Product Overview

The SN74LVC1G86DCKR is a single 2-input exclusive-OR (XOR) gate from Texas Instruments for 1.65V to 5.5V operation. It performs Y = A⊕B in positive logic: output is high when inputs differ. If one input is low, the other passes through in true form; if one input is high, the other is inverted. This versatile function enables parity generation, controlled inversion, and comparison logic. Features 4ns max tpd, ±24mA drive, 5.5V OVT inputs, and Ioff.

Key Specifications

Logic Function XOR (Y = A⊕B = ĀB + AB̄)
Supply Voltage 1.65V to 5.5V
Propagation Delay (tpd) 4ns max @ 3.3V, 15pF load
Output Drive ±24mA @ 3.3V; ±32mA @ 4.5V
Quiescent Current (ICC) 10µA max
Input Voltage Tolerance Up to 5.5V (overvoltage tolerant)
Down Translation Yes
Ioff Support Yes
ESD Protection 2000V HBM, 1000V CDM
Latch-Up >100mA per JESD 78 Class II
Package SC70-5 / SOT-353 (2.0 x 1.25mm)
Operating Temperature -40°C to +125°C

Features

  • Exclusive-OR function: Y = A⊕B
  • 1.65V to 5.5V VCC operation
  • 5.5V overvoltage-tolerant inputs
  • 4ns max propagation delay at 3.3V
  • 10µA max quiescent current
  • ±24mA output drive at 3.3V
  • Controlled inversion: one input selects true/invert
  • Ioff for partial-power-down support
  • Five equivalent XOR symbol representations
  • NanoFree package available

Applications

  • Controlled signal inversion (true/complement)
  • Parity generation and checking
  • Phase detection and comparison
  • Data scrambling/descrambling
  • Edge detection (change detection)
  • BPSK modulation control

The SN74LVC1G86DCKR is a single 2-input exclusive-OR (XOR) gate from Texas Instruments’ LVC family, designed for 1.65V to 5.5V VCC operation. It performs Y = A⊕B (equivalently Y = ĀB + AB̄) in positive logic. The XOR function outputs high when the two inputs are different. A key property: if one input is held low, the other input passes through in true form (buffering); if one input is held high, the other input appears inverted at the output. This ‘controlled inversion’ makes the XOR gate invaluable for BPSK modulation, data scrambling, and selectable true/complement signal routing. The device supports 5.5V overvoltage-tolerant inputs, down-translation, and Ioff partial-power-down isolation.

The SN74LVC1G86 implements the XOR function using a CMOS transmission-gate-based design. When input A is low, transmission gates route input B directly to the output (true form). When input A is high, transmission gates route input B inverted to the output. This implementation is more compact and faster than the classic AND-OR-INVERT approach. The truth table is: A=0,B=0→Y=0; A=0,B=1→Y=1; A=1,B=0→Y=1; A=1,B=1→Y=0. The output is high exactly when inputs differ. Overvoltage-tolerant inputs use isolation transistors, and the Ioff circuit disconnects the output when VCC is removed for safe partial-power-down operation.

Pin Name Description
1 1A Input A
2 1B Input B
3 GND Ground
4 Y Output (Y = A⊕B)
5 VCC Supply voltage (1.65V to 5.5V)
  • Controlled Inverter (BPSK): Connect a data signal to input A and a modulation/control signal to input B. When B=0, Y=A (data passes through). When B=1, Y=Ā (data is inverted). This is the basis of binary phase-shift keying (BPSK) modulation and data scrambling. A single XOR gate implements the complete function.
  • Parity Generator: Cascade XOR gates to compute the parity of a multi-bit data word. For 8-bit parity, XOR bits 0-1, then XOR the result with bit 2, and so on. The final output is the parity bit. The 4ns propagation delay supports high-speed parity computation in communication protocols.
  • Edge/Change Detector: Connect a signal to input A and a delayed version of the same signal (via RC or buffer delay) to input B. The XOR output pulses high during the transition when A and B differ, detecting edges (both rising and falling). The pulse width equals the delay, adjustable by the RC time constant.
Model Function Key Difference
SN74LVC1G86DBVR XOR gate SOT-23-5, larger package
SN74LVC2G86DCTR Dual XOR 2 channels, VSSOP-8
74AUP1G86GF XOR gate Nexperia, 0.8V min, ultra-low power
NC7SZ86P5X XOR gate Renesas/IDT, similar specs
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