PCA9617ADP

The PCA9617A is an I2C-bus repeater from NXP that provides both voltage level translation and bus capacitance isolation between two I2C bus segments. The PCA9617ADP is the TSSOP-8 packaged version, which is a footprint and functional replacement for the PCA9517A at Fast-mode speeds, with the added benefit of Fast-mode Plus (1 MHz) support.

The device has two ports with different voltage and signaling characteristics. Port A operates from 0.8 V to 5.5 V with normal CMOS logic levels — its output pulls down to near 0 V (hard low) and its input threshold is 0.35 × VCC(A). Port B operates from 2.2 V to 5.5 V with a static offset of approximately 0.55 V — its output pulls down to only 0.55 V, and its input threshold is about 0.45 V. The offset design prevents latch-up: when Port B internally drives low at 0.55 V, its own input (threshold 0.45 V) does not recognize this as a valid low, preventing the device from holding itself in a low state.

The key benefit of the PCA9617A is bus capacitance isolation. Each port of the repeater presents only about 7 pF of capacitance to its respective bus, regardless of the capacitance on the other side. This allows system designers to create large I2C networks well beyond the 400-pF specification limit. At 1 MHz (Fm+), each side can support up to 540 pF; at lower speeds, each side can support up to 4000 pF.

The level translation works in both directions without direction pins — the open-drain I2C bus architecture inherently supports this. A low on Port A (below 0.3 × VCC(A)) turns on the Port B pull-down. A low on Port B (below 0.4 V) turns on the Port A pull-down. This bidirectional operation is transparent to the I2C protocol, including arbitration, clock stretching, and multi-master scenarios.

The EN (enable) pin is active-high, referenced to VCC(B). When EN is low, both port drivers are disabled and all I/O pins are high-impedance. The device is enabled only when VCC(A) > 0.8 V and VCC(B) > 2.2 V, with a ~400 µs power-up delay for internal reference settling.

The PCA9617A is included in NXP’s 15-year product longevity program, making it suitable for long-lifecycle industrial and automotive applications.

**Bidirectional Open-Drain Buffering:** The PCA9617A implements two identical channels (SDA and SCL), each consisting of a pair of open-drain buffers connected back-to-back between Port A and Port B. Because I2C is an open-drain bus, there is no need for direction control signals — the bus itself determines the direction of data flow.

**Port A to Port B Translation:** When a device on Port A pulls SDA_A below 0.3 × VCC(A), the Port B driver activates and pulls SDA_B down to approximately 0.55 V (not to 0 V, due to the static offset). When SDA_A rises above the threshold, the Port B driver releases and the external pull-up resistor on SDA_B pulls it high.

**Port B to Port A Translation:** When a device on Port B pulls SDA_B below 0.4 V, the Port A driver activates and pulls SDA_A down to near 0 V (hard low). When SDA_B rises above 0.4 V, the Port A driver releases. The hard low on Port A is critical for low-voltage operation, as it maximizes the noise margin at 0.8 V.

**Static Offset and Latch Prevention:** The 0.55-V offset on Port B means that when the PCA9617A internally drives Port B low, the resulting 0.55-V level is above the Port B input threshold (0.45 V? — no, the internal buffer input is 90 mV below the output, at ~0.45 V). Actually, the input threshold is set 90 mV below the output pull-down level: output drives to 0.55 V, input threshold is 0.45 V. So the internally generated 0.55 V is NOT recognized as a low by the input (since it’s above 0.45 V). This prevents the latch condition where the device would hold itself low indefinitely.

**Capacitance Isolation:** Each port presents only ~7 pF loading to its bus. The buffering action means that the capacitance on one bus does not add to the other. Rise times on each bus are determined only by the pull-up resistor and capacitance on that side, not by the total system capacitance.