NC7SZ66P5X

The NC7SZ66 from onsemi’s TinyLogic UHS family is a single-bit SPST bus switch in an ultra-small SC-70-5 package. The NC7SZ66P5X is the tape-and-reel version with 3000 units per reel. Originally designed by Fairchild Semiconductor (now part of onsemi), the device provides a low-impedance pass-through path between two ports with minimal propagation delay.

When the output enable (OE) pin is HIGH, the switch closes and port A connects to port B through approximately 5 Ω. When OE is LOW, the switch opens and a high-impedance state exists between the two ports. The switch handles signals from 0 V to VCC (rail-to-rail), and the 5 Ω on-resistance introduces negligible voltage drop for typical logic signals.

The key advantage of a bus switch over a buffer is zero propagation delay contribution other than the RC delay through the on-resistance and load capacitance. At 5 V, the propagation delay through the switch is typically 0.3 ns, making it essentially transparent to timing budgets.

The device supports over-voltage tolerant inputs up to 7 V, enabling voltage translation between different logic domains. When VCC is 0 V, all I/O pins enter a high-impedance state, preventing backflow current in partially-powered systems — critical for hot-swap and power-sequencing applications.

The NC7SZ66 is available in three packages: SC-70-5 (P5X), SOT-23-5 (M5X), and MicroPak-6 (L6X). The SC-70-5 version occupies only 2.5 mm² of board area.

Note: Some distributors list the NC7SZ66P5X as obsolete, but it remains available from multiple sources. Verify current availability before designing into new products.

**CMOS Transmission Gate:** The NC7SZ66 uses a CMOS transmission gate (parallel NMOS + PMOS) as the switch element. The NMOS passes signals near VCC well, while the PMOS passes signals near GND well. Together, they provide rail-to-rail signal handling with a relatively flat on-resistance across the full voltage range. The typical 5 Ω on-resistance is the parallel combination of both transistors.

**OE Control Logic:** When OE is HIGH, both the NMOS and PMOS gates are driven to turn on their respective transistors, creating a low-impedance path between A and B. When OE is LOW, both transistors turn off, isolating the two ports with high impedance and low off-state leakage (< 1 nA typical). **Over-Voltage Tolerance:** Input and I/O pins incorporate circuitry that tolerates voltages up to 7 V independently of VCC. When a voltage above VCC appears on a switch port, the internal ESD diode to VCC is reverse-biased, preventing current flow into the VCC rail. **Power-Off High-Impedance:** When VCC is 0 V, an internal circuit disables the switch and places all I/O in high-impedance, preventing any current path between ports or into the supply. This enables hot-swap and live-insertion applications.