LPC1768FBD100

The LPC1768FBD100 from NXP Semiconductors is the flagship member of the LPC176x/5x family of ARM Cortex-M3 microcontrollers, offering the maximum memory density (512 KB Flash / 64 KB SRAM) and the full peripheral set in a 100-pin LQFP package. It is one of the most popular and widely-deployed Cortex-M3 MCUs in the industry, with a mature ecosystem and extensive software support.

The LPC1768 is significant because it was one of the first Cortex-M3 devices to integrate Ethernet MAC, USB 2.0, and CAN in a single chip, targeting industrial networking, motor control, and smart metering applications that previously required multiple chips or a higher-end ARM9 processor. The pin-compatibility with the older LPC2368 (ARM7TDMI) allows easy migration from ARM7 to Cortex-M3 with only software changes.

The ARM Cortex-M3 core runs at up to 100 MHz and achieves 1.25 DMIPS/MHz (125 DMIPS at 100 MHz). The 3-stage pipeline with speculative branch prefetch provides efficient instruction throughput. The built-in NVIC supports up to 33 interrupt vectors with 8 programmable priority levels, enabling deterministic real-time interrupt handling. The MPU allows privileged software to define 8 memory regions with individual access permissions, protecting critical data from corruption by unprivileged code.

The 512 KB Flash provides ample code storage for complex applications including TCP/IP stacks, USB device stacks, CAN protocol stacks, and motor control algorithms. The Flash supports in-system programming (ISP) via UART and in-application programming (IAP) for firmware updates, data logging, and boot loader implementation. The 64 KB SRAM is sufficient for large application data structures, network buffers, and USB endpoint buffers.

The 8-channel GPDMA is a key performance feature that allows data transfers between peripherals and memory without CPU intervention. Each DMA channel can be triggered by UART, SSP, I2S, ADC, DAC, timer match events, or external DMA requests. The multilayer AHB matrix provides separate bus paths for the CPU, DMA, Ethernet, and USB, eliminating arbitration delays and allowing concurrent bus transactions. This architecture enables the CPU to execute code from Flash while the DMA simultaneously transfers Ethernet packets and USB data.

The Ethernet MAC with RMII interface and dedicated DMA controller provides full 10/100 Mbps Ethernet capability. The MAC implements the IEEE 802.3 MAC layer including CRC generation/checking, frame filtering, and flow control. The dedicated DMA engine handles frame reception and transmission autonomously, reducing CPU overhead for network communication. An external PHY chip (such as DP83848 or LAN8720) is required to complete the physical layer.

The USB 2.0 full-speed controller supports Device, Host, and OTG modes. In Device mode, it supports up to 16 endpoints (in addition to EP0) with dedicated DMA. In Host mode, it can enumerate and communicate with USB peripherals. The OTG mode allows the device to act as either host or peripheral. The on-chip PHY eliminates the need for an external USB transceiver.

The dual CAN 2.0B controller is essential for automotive and industrial applications. Each channel supports standard (11-bit) and extended (29-bit) identifiers, with individual acceptance filters. The CAN controller handles bit timing, stuffing, CRC, and error management in hardware, reducing CPU overhead.

The motor control PWM supports 3-phase motor drive with complementary PWM outputs, dead-time generation, and fault protection inputs. Combined with the ADC (which can be synchronized to the PWM for current sampling) and the quadrature encoder interface, the LPC1768 provides a complete motor control subsystem.

The 4 low-power modes (Sleep, Deep-sleep, Power-down, Deep power-down) with the Wake-up Interrupt Controller (WIC) enable battery-powered applications. In Deep power-down mode, the RTC can remain operational from the VBAT supply while the rest of the chip is powered down, consuming only a few microamps.

The mbed platform (now part of Arm) originally launched with the LPC1768 as its reference MCU, and the mbed online compiler and HDK were designed around it. This gives the LPC1768 one of the largest collections of open-source libraries and example code among Cortex-M3 devices. The device is also supported by NXP’s MCUXpresso IDE, Keil MDK, IAR Embedded Workbench, and GCC-based toolchains.

The LPC1768FBD100 operates as a complete 32-bit embedded microcontroller system centered on the ARM Cortex-M3 processor core with a multilayer AHB bus matrix providing high-bandwidth data paths between masters and slaves.

ARM Cortex-M3 Core: The Cortex-M3 is a 32-bit RISC processor implementing the ARMv7-M architecture with the Thumb-2 instruction set. Unlike the older ARM7TDMI (which uses the ARM/Thumb instruction sets), the Cortex-M3 exclusively uses the mixed 16/32-bit Thumb-2 instruction set, achieving higher code density. The 3-stage pipeline (Fetch, Decode, Execute) with branch speculation provides single-cycle execution for most 16-bit instructions. The processor includes a hardware divide instruction (2-12 cycles), bit-band support for atomic bit manipulation, and unaligned memory access support.

NVIC and Interrupt Handling: The Nested Vectored Interrupt Controller supports up to 33 interrupt vectors with 8 priority levels. On interrupt, the processor automatically pushes 8 registers (R0-R3, R12, LR, PC, xPSR) to the stack in 12 cycles, and automatically pops them on return in 12 cycles. This tail-chaining and late-arrival optimization ensures deterministic interrupt latency. The WIC (Wake-up Interrupt Controller) allows the processor to wake from Deep-sleep and Power-down modes on any enabled interrupt without CPU intervention.

Multilayer AHB Matrix: The bus matrix provides 4 separate AHB buses for the 4 bus masters: CPU, DMA, Ethernet, and USB. Each master can access any slave (Flash, SRAM, peripheral registers) independently, without stalling other masters. The split APB bus allows the CPU and DMA to access different APB peripherals simultaneously. This architecture is critical for the Ethernet and USB DMA controllers to sustain high-throughput data transfers without impacting CPU execution.

Memory Map: The Cortex-M3 defines a fixed memory map. The Flash is mapped at 0x00000000 (code space), SRAM at 0x10000000 (data space), and peripherals at 0x40000000 (APB) and 0x50000000 (AHB). The bit-band region maps each bit in the 0x20000000 (SRAM) and 0x40000000 (peripheral) regions to a word address in the bit-band alias region, enabling atomic bit set/clear operations without read-modify-write sequences.

Clock System: The main oscillator (1-25 MHz external crystal) or the 4 MHz internal RC oscillator feeds the PLL0 which multiplies the frequency to generate the CPU clock (up to 100 MHz), the USB clock (48 MHz from PLL1), and the peripheral clocks. Each peripheral has its own clock divider, allowing unused peripherals to be clocked slowly or not at all to save power. The clock output function (CLKOUT) can reflect any internal clock on an external pin for debugging.

Power Management: The 4 power modes reduce power consumption progressively. Sleep mode stops the CPU clock but keeps all peripherals running; any interrupt wakes the CPU. Deep-sleep mode stops the Flash and most clocks; only the RTC, WDT, and BOD can generate wake-up interrupts. Power-down mode stops all internal clocks and the Flash; the WIC remains active and can wake the processor from external interrupts, RTC, USB activity, Ethernet wake-up, or CAN activity. Deep power-down mode turns off the entire chip except the RTC (powered from VBAT) and the WIC; current consumption is approximately 0.3 uA. The integrated PMU manages the power mode transitions automatically.

DMA Operation: The GPDMA supports 8 channels, each independently configurable for source/destination address, transfer size, burst size, and flow control. The DMA can perform memory-to-memory, memory-to-peripheral, and peripheral-to-memory transfers. Each peripheral that supports DMA (UART, SSP, I2S, ADC, DAC, timer match) has dedicated DMA request lines connected to the DMA controller. The DMA controller arbitrates between channels on a priority basis and generates an interrupt when a transfer completes or encounters an error.

Ethernet MAC: The MAC implements the IEEE 802.3 MAC layer with DMA. Received frames are stored in SRAM buffers pointed to by descriptor rings. The DMA engine manages the descriptor ring autonomously, fetching new descriptors and storing received data. Transmit frames are similarly described by descriptor rings. The MAC performs address filtering (promiscuous, hash, or exact match), VLAN tag detection, and frame checksum verification. The RMII interface connects to an external PHY chip with only 7 signals (REF_CLK, TXD[0:1], TX_EN, RXD[0:1], RX_ER, CRS_DV).

ADC and DAC: The 12-bit ADC uses a successive approximation register (SAR) architecture with a conversion time of approximately 2.4 us per channel at 200 kHz rate. The ADC can be triggered by timer match events for precise periodic sampling, or by the motor control PWM for synchronized motor current measurement. The 10-bit DAC uses an R-2R ladder network with a settling time of approximately 1 us. The DAC output can be synchronized to a timer for waveform generation, or driven by the DMA for arbitrary waveform output.