The LPC1764FBD100K is an ARM Cortex-M3 microcontroller from NXP in LQFP-100, running at 96MHz with 64KB Flash and 16KB SRAM. It is the entry-level member of the LPC176x family, which is widely used in industrial and embedded applications. The Cortex-M3 core implements the ARMv7-M architecture with a 3-stage pipeline, hardware multiply (1-cycle), hardware divide (2-12 cycles), and NVIC (Nested Vectored Interrupt Controller) supporting up to 32 interrupts with 8 priority levels. The LPC1764 includes three USARTs (UART0/2/3), two SPI/SSP ports, three I2C interfaces, and a 12-bit ADC with 8 channels and 200ksps conversion rate. The four general-purpose timers (TIM0-3) support capture, match, and PWM modes. The two CAN 2.0B controllers support Full-CAN with acceptance filtering. The 10/100 Ethernet MAC (not PHY) supports MII/RMII interfaces to an external PHY like the LAN8720A. The USB 2.0 Full-Speed device/OTG controller provides 32 endpoints. The AHB bus matrix allows concurrent DMA transfers between peripherals and SRAM without stalling the CPU. The internal RC oscillator is trimmed to 1% accuracy at 12MHz. The ISP (In-System Programming) bootloader allows firmware updates via UART without a debugger.