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HEF4094BT

8-bit shift register, 3-15V, latched 3-state outputs, cascade QS/QS', serial-to-parallel, SOIC-16

6200

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Pieza del fabricante：

HEF4094BT

Paquete：

SOIC-16 (10.3 x 5.3 x 1.75mm)

Descripción

Productos

The HEF4094BT is an 8-stage serial shift register with output latches and 3-state outputs from Nexperia. Data is shifted in serially on the rising edge of the clock and transferred to the output latches on the rising edge of the strobe (STR). The 3-state outputs (QP0-QP7) can drive bus lines directly, while the serial output (QS) enables cascading. Operating from 3V to 15V, it suits display driving, LED control, and serial-to-parallel data conversion in SOIC-16.

Especificaciones

Función	8-bit shift register with latched 3-state outputs
Stages	8 (serial-in, parallel-out)
Tensión de alimentación	3V to 15V
Clock Frequency	Up to 12MHz @ 10V
Retardo de propagación	95ns typ @ 10V
Output Drive	±3.4mA @ 10V; ±6.8mA @ 15V
Output Type	3-state (QP0-QP7); push-pull (QS, QS’)
Output Latch	Yes (STR pin controls latch)
Cascade Output	QS (after 8th stage) and QS’ (after 9th stage)
Corriente de reposo	20µA max @ 20V
Paquete	SOIC-16 (10.3 x 5.3mm)
Temperatura de funcionamiento	-40°C to +125°C

Características

8-bit serial-in, parallel-out shift register
Output latches with separate strobe control
3-state parallel outputs for bus driving
Serial cascade outputs (QS and QS’) for daisy-chaining
3V to 15V supply range
Shift and latch operate independently
Up to 12MHz clock rate at 10V
Standard CD4000B CMOS logic family

Aplicaciones

LED display driving (7-segment, bar graph)
Serial-to-parallel data conversion
Multi-channel relay/solenoid control
GPIO expansion via serial interface
Instrumentation display multiplexing
Cascaded display panels

Introducción del producto:HEF4094BT Presentación del producto

The HEF4094BT from Nexperia is an 8-stage serial shift register with storage registers and 3-state outputs, part of the HEF4000B logic family. Data is clocked into the 8-bit shift register on the rising edge of the clock (CP). The rising edge of the strobe (STR) transfers the shift register data to the 8-bit storage register, which drives the QP0-QP7 outputs. The 3-state outputs can be enabled or disabled via the output enable (OE) pin, allowing direct connection to bus lines. The QS output provides the shift register data after the 8th stage, and QS’ provides data after the 9th stage — both useful for cascading multiple HEF4094 devices. The separation of shift and storage clocks allows updating the display without flicker. The wide 3-15V supply range suits industrial and automotive applications.

Principio de funcionamiento:HEF4094BT Principio de funcionamiento

The HEF4094BT contains two 8-bit registers: a shift register and a storage (latch) register. On each rising edge of CP, the serial data at the D input is shifted into the first stage, and all existing data shifts one position toward the 8th stage. After 8 clock cycles, the first data bit appears at the 8th stage and is available at the QS cascade output. The QS’ output provides the 9th stage data for extended cascading. When STR goes high, the current contents of the shift register are transferred to the storage register. The storage register outputs (QP0-QP7) reflect this data when OE is high (3-state enabled). When OE is low, the outputs go to high-impedance. The separation of shift and latch clocks means the display can be updated without visible flicker: new data is shifted in (potentially taking many clock cycles), then latched to the outputs in a single STR pulse.

Descripción de la clavija:HEF4094BT Definición y funciones de las clavijas

Pin	Nombre	Descripción
1	STR	Strobe input (rising edge latches data)
2	D	Entrada de datos serie
3	CP	Clock input (rising edge shifts data)
4	OE	Output enable (high = outputs active, low = Hi-Z)
5	QP4	Parallel output bit 4
6	QP5	Parallel output bit 5
7	QP6	Parallel output bit 6
8	QP7	Parallel output bit 7
9	QS	Serial cascade output (after 8th stage)
10	QS’	Serial cascade output (after 9th stage)
11	QP0	Parallel output bit 0
12	QP1	Parallel output bit 1
13	QP2	Parallel output bit 2
14	QP3	Parallel output bit 3
15	VSS	Suelo
16	VDD	Positive supply (3V to 15V)

Application Scenarios:In which products and applications isHEF4094BT usado

Cascaded LED Display Panel: Cascade three HEF4094BT devices to drive a 24-LED bar graph display. Connect QS from the first device to D of the second, and so on. Shift in 24 bits of LED state data (3 bytes), then pulse STR to update all displays simultaneously without flicker. The 3-state outputs allow the display to be disabled (OE low) during data loading for a blank-then-update display sequence.
7-Segment Display Multiplexing: Use one HEF4094BT per digit in a multi-digit 7-segment display. Each device drives one digit’s segments (a-g plus DP). All devices share CP, STR, and OE lines. Data is cascaded through QS. This creates a 3-wire serial interface (D, CP, STR) to control any number of digits, saving MCU GPIO pins.
Industrial Relay Controller: Control 8 relays or solenoid valves from an MCU using only 3 pins (D, CP, STR). The 15V supply range allows direct connection to 12V industrial relay coils through external driver transistors. The 3-state outputs can be wire-ORed with other data sources on a shared control bus. Cascade multiple devices for 16 or 24 channels of control.

Alternative Models:What chips are recommended as replacements for HEF4094BT

Modelo	Bits	VDD	Diferencia clave
CD4094BM96	8	3-18V	TI version, higher voltage
74HC595D	8	2-6V	Nexperia, low-voltage, more popular
74HCT595D	8	4.5-5.5V	Nexperia, TTL input thresholds
TPIC6B595	8	4.5-5.5V	TI, 50V/150mA DMOS outputs