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CD4015BE

Dual 4-bit SIPO shift register, common CLK, independent reset, CMOS 3-18V, PDIP-16

3000

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Pieza del fabricante：

CD4015BE

Paquete：

PDIP-16 (19.3 x 9.4 x 4.57mm, 2.54mm pitch, through-hole)

Marca：

Categorías de productos：

Circuitos integrados IC, Circuitos integrados de interfaz

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Descripción

Productos

The CD4015BE from Texas Instruments contains two independent 4-bit serial-in parallel-out shift registers with common clock and independent reset — a dual CD4014-like device in a 16-pin PDIP package.

Especificaciones

Función	Dual 4-bit serial-in parallel-out shift register
Technology	CD4000B CMOS
Tensión de alimentación	3V to 18V
Register Length	4 bits each (2 independent registers)
Serial Input	DATA (per register)
Outputs	Q1, Q2, Q3, Q4 (per register, all accessible)
Restablecer	Asynchronous, active HIGH (MR, per register)
Max Clock Frequency	6MHz @ VDD=10V
Temperatura de funcionamiento	-55°C to +125°C
Paquete	PDIP-16 (19.3 x 9.4mm)

Características

Two independent 4-bit shift registers
Common clock (CLK) for both registers
Independent data inputs and resets
All 4 outputs accessible per register
Cascadable: Q4 → DATA of next register
3V-18V wide supply range

Aplicaciones

Serial-to-parallel conversion
LED chaser / display driving
Temporary data storage
Time delay circuits

Introducción del producto:CD4015BE Presentación del producto

The CD4015BE from Texas Instruments contains two independent 4-bit serial-in parallel-out shift registers sharing a common clock. Each register has its own DATA input, MR (master reset), and four parallel outputs (Q1-Q4). On each rising clock edge, the DATA input is shifted into Q1, and Q1→Q2→Q3→Q4 in a ripple fashion. When MR is HIGH, all outputs are forced to 0 asynchronously. The common clock means both registers shift simultaneously — useful for dual-channel applications where two data streams must be synchronized. The two registers can also be cascaded: Q4 of register 1 connects to DATA of register 2, creating an 8-bit shift register. Unlike the CD4094, the CD4015 has no output latch — outputs change as data shifts through, which is fine for LED chasers but may cause flicker in display applications requiring stable outputs. The CD4015 is simpler and lower-cost than the CD4094 for applications that don’t need latched outputs. The BE suffix denotes the PDIP-16 package.

Principio de funcionamiento:CD4015BE Principio de funcionamiento

Each 4-bit shift register in the CD4015BE operates as follows: on each rising CLK edge, DATA is loaded into Q1, and all other bits shift one position (Q1→Q2, Q2→Q3, Q3→Q4). The old Q4 data is lost (or passed to a cascaded register). When MR (master reset) is HIGH, all four outputs (Q1-Q4) are forced to 0 immediately regardless of CLK and DATA. For normal shifting, MR must be LOW. To load 4 bits: shift 4 clock cycles with the desired data on DATA; after 4 clocks, Q1=last bit shifted, Q4=first bit shifted. For cascading: Q4 of register 1 → DATA of register 2; shared CLK; after 8 clocks, register 2 has the first 4 bits and register 1 has the last 4 bits — an 8-bit SIPO. Both registers shift on the same clock edge, so dual data streams can be processed in parallel. The CD4015 is essentially half a CD4014 (8-bit) with separate resets and no parallel load capability.

Descripción de la clavija:CD4015BE Definición y funciones de las clavijas

Pin	Nombre	Tipo	Descripción
1	Q4A	Salida	Register A output bit 4 (MSB)
2	Q3A	Salida	Register A output bit 3
3	Q2A	Salida	Register A output bit 2
4	Q1A	Salida	Register A output bit 1 (LSB, first stage)
5	CLK	Entrada	Common clock (positive edge)
6	MRA	Entrada	Register A master reset (active HIGH)
7	DATA A	Entrada	Register A serial data input
8	VSS	Potencia	Suelo
9	DATA B	Entrada	Register B serial data input
10	MRB	Entrada	Register B master reset (active HIGH)
11	Q1B	Salida	Register B output bit 1 (LSB)
12	Q2B	Salida	Register B output bit 2
13	Q3B	Salida	Register B output bit 3
14	Q4B	Salida	Register B output bit 4 (MSB)
15	VDD	Potencia	Supply (3V to 18V)
16	NC	—	No connection

Application Scenarios:In which products and applications isCD4015BE usado

8-Bit SIPO: Q4A → DATA B; shared CLK; shift 8 bits → 8 parallel outputs from 2 MCU pins
Dual 4-LED Chaser: Two independent LED patterns on Q1A-Q4A and Q1B-Q4B; same CLK; different data streams
4-Bit Time Delay: Signal on DATA A; Q1A = 1 clock delay, Q2A = 2, Q3A = 3, Q4A = 4 clock delays
Serial-to-Parallel: MCU serial data → DATA A; CLK from MCU; Q1A-Q4A = 4-bit parallel output after 4 clock cycles

Alternative Models:What chips are recommended as replacements for CD4015BE

Modelo	Fabricante	Diferencia clave	Paquete	Supply
CD4015BM	TI	SOIC-16 surface-mount version with identical logic function and 3-18V range	SOIC-16	3-18V
CD4015BE	TI	Through-hole DIP version for prototyping and legacy board repair	DIP-16	3-18V
HEF4015BT	NXP	Pin-compatible CMOS version with improved ESD protection and 3-15V supply	SOIC-16	3-15V
MC144015BDR2G	onsemi	Pin-compatible equivalent with RoHS compliance and AEC-Q100 automotive option	SOIC-16	3-18V
74HC164D	TI/Nexperia	HC CMOS version with higher speed and 2-6V supply for modern logic systems	SOIC-16	2-6V
74HC164N	TI/Nexperia	HC CMOS through-hole version for prototyping with 2-6V supply range	DIP-16	2-6V
74HCT164D	Nexperia	HCT version with TTL-compatible inputs for mixed 5V TTL/CMOS systems	SOIC-16	4.5-5.5V

CD4015 is the CMOS 4000-series dual 4-bit serial-in/parallel-out shift register operating over the wide 3-18V supply range. The HEF4015 (NXP) and MC144015 (onsemi) are direct pin-compatible equivalents. For higher speed at the cost of narrower voltage range, the 74HC164 HC/HCT families offer significantly faster propagation delay and lower power consumption at 2-6V. Surface-mount versions use the BM/M suffix (SOIC); through-hole versions use the BE suffix (DIP).