TXS0102DCUR

The TXS0102DCUR is a 2-bit bidirectional voltage-level translator from Texas Instruments designed for mixed-voltage systems where I²C, UART, GPIO, or other digital signals must cross between different voltage domains. It requires no direction-control signal — each channel automatically senses and translates in both directions, simplifying board design.

The A port operates from 1.65 V to 3.6 V (tracking VCCA), and the B port operates from 2.3 V to 5.5 V (tracking VCCB), with the constraint VCCA ≤ VCCB. This covers all common logic voltage combinations: 1.8 V-to-3.3 V, 1.8 V-to-5 V, 3.3 V-to-5 V, and 2.5 V-to-3.3 V.

The TXS architecture uses passive pass-transistor switches with edge-rate accelerators. For open-drain buses (I²C, SMBus), the pass-FET provides a low-impedance path and the one-shot accelerator briefly turns on a strong pull-up to speed rising edges, achieving up to 2 Mbps. For push-pull signals (UART, SPI, GPIO), the accelerator provides fast edges up to 24 Mbps.

The VCC isolation feature ensures that if either VCCA or VCCB is at GND, both ports enter a high-impedance state, preventing back-feeding. The Ioff circuitry supports partial-power-down mode, allowing one side to be powered down while the other remains active without leakage. No power-supply sequencing is required — either rail can ramp first.

ESD protection is asymmetric: the A port provides 2.5-kV HBM, while the B port (facing the higher-voltage, often external-facing side) provides 8-kV HBM. The OE pin, when pulled low, places all I/Os in high-impedance state with reduced quiescent current. The VSSOP-8 (DCU) package occupies only 4.6 mm² of board area, making it ideal for space-constrained portable designs.

**Pass-FET Switch Core:** Each channel consists of an N-channel pass transistor connecting the A and B sides. The pass-FET gate is biased at a voltage between VCCA and VCCB, allowing bidirectional current flow when either side drives low. The on-resistance is approximately 10 Ω, providing a low-impedance path for DC and low-frequency signals.

**Edge-Rate Accelerator:** One-shot circuits on each side detect falling edges and briefly turn on a strong pull-down (≈ 30 mA for ~30 ns) to accelerate the transition. For rising edges on open-drain buses, the accelerator briefly turns on a strong pull-up to overcome the weak external pull-up resistor. This enables 2 Mbps on I²C at 3.3-V/5-V translation.

**Auto-Direction Detection:** The TXS translator has no explicit direction control. The pass-FET inherently allows either side to drive the bus low. When neither side is driving, the external pull-up resistors (for open-drain) or the driving device (for push-pull) pull the line high through the pass-FET. This transparent operation eliminates the need for a DIR pin.

**VCC Isolation and Ioff:** When either supply is at GND, an internal circuit detects the condition and opens the pass-FET, placing both I/Os in high-impedance. The Ioff feature ensures that no leakage current flows from the powered side to the unpowered side, which is critical for hot-swap and battery-backup applications.