The ADS8320E/2K5 is a 16-bit 100kSPS SAR (Successive Approximation Register) ADC from TI in VSSOP-8, operating from 2.7V to 5.25V with SPI-compatible serial interface. The SAR conversion algorithm works by: 1) Sample the analog input on an internal hold capacitor (conversion starts on CS falling edge); 2) The 16-bit SAR register starts at MSB = 1, all others = 0; 3) The internal DAC converts this digital code to an analog voltage; 4) The comparator determines if the DAC output is higher or lower than the held input; 5) If DAC > input, MSB = 0; if DAC < input, MSB stays 1; 6) Repeat for each bit from MSB to LSB (16 comparisons total). The entire conversion takes 16 DCLK cycles plus 2 overhead cycles = 18 DCLK periods. At 2.4MHz DCLK, this gives 100kSPS throughput. The external VREF pin sets the full-scale range: VIN ranges from COM to VREF. Using a 2.5V reference gives 0-2.5V input range with 38uV LSB step size (2.5V / 65536). The /2K5 suffix denotes the 100kSPS speed grade and tape-and-reel packaging. The SHDN pin (active LOW) reduces power from 4.5mW to 0.3uW. The SPI interface is compatible with most MCUs: CS frames the conversion, DCLK shifts out data on DOUT MSB-first, with the first clock outputting the MSB result of the previous conversion.