ADP1755ACPZ-R7

The ADP1755ACPZ-R7 from Analog Devices is a 1.2 A, low input voltage, adjustable output voltage, low dropout (LDO) linear regulator designed for powering noise-sensitive loads such as FPGAs, DSPs, microprocessors, and data converters from low-voltage input rails.

The ADP1755 is specifically optimized for low input/output voltage applications. The input voltage range of 1.6 V to 3.6 V means it is designed to regulate from common intermediate bus voltages such as 1.8 V, 2.5 V, and 3.3 V, and produce output voltages as low as 0.75 V. This makes it ideal for powering the core voltages of modern FPGAs and processors (0.9 V, 1.0 V, 1.1 V, 1.2 V) from a 1.8 V or 2.5 V rail.

The ADP1755 is the adjustable version of the ADP1754/ADP1755 family. The ADP1754 offers seven fixed output voltage options (0.75 V, 0.8 V, 0.9 V, 1.0 V, 1.2 V, 1.5 V, 2.5 V) for simplicity, while the ADP1755 allows any output voltage from 0.75 V to 3.3 V via an external resistor divider connected to the ADJ pin. The adjustable version is preferred when the output voltage is non-standard, when a single SKU must support multiple voltage rails, or when the output voltage must be fine-tuned.

The 0.5 V reference voltage at the ADJ pin means the output voltage is set by the formula VOUT = 0.5 V x (1 + R1/R2), where R1 is the upper resistor and R2 is the lower resistor. The low reference voltage enables output voltages close to 0.5 V, but the minimum guaranteed output voltage is 0.75 V due to the headroom required for the error amplifier and feedback network.

The 105 mV dropout voltage at 1.2 A is exceptionally low for a CMOS LDO, corresponding to an effective RDS(on) of approximately 88 mOhm. This allows the ADP1755 to regulate from a 1.8 V input down to a 1.5 V output at full 1.2 A load with only 105 mV of headroom. For a 1.2 V output at 1.2 A, the minimum input voltage is approximately 1.305 V, allowing regulation from a 1.5 V or 1.8 V rail.

The high PSRR of 65 dB at 1 kHz and 54 dB at 100 kHz makes the ADP1755 effective at rejecting switching power supply ripple and noise on the input rail. This is critical for FPGA and data converter applications where power supply noise directly impacts signal integrity and timing jitter. When the ADP1755 is used as a post-regulator after a switching converter, the combined PSRR can exceed 100 dB at 1 kHz, effectively eliminating switching ripple from the supply.

The 23 uV RMS output noise at 0.75 V output is very low for a 1.2 A LDO, ensuring that the regulated supply does not degrade the performance of noise-sensitive analog circuits such as ADCs and DACs. For even lower noise, an additional RC filter or ferrite bead can be added at the output, but in many applications the 23 uV RMS noise is sufficient without additional filtering.

The programmable soft start feature prevents inrush current during power-up. An external capacitor on the SS pin sets the startup ramp time; the soft start time is approximately 1 ms per 10 nF of capacitance. Without an external capacitor, the internal default soft start is active. Soft start is particularly important when the LDO is powering large FPGA core decoupling capacitor banks (10-100 uF) that would otherwise draw excessive inrush current.

The power-good (PG) output is an open-drain output that goes high-impedance when the output voltage is within the regulation window (typically above 90 percent of the set voltage). The PG output can be used to enable downstream loads, signal the system controller, or daisy-chain multiple LDO power-good signals for sequential power-up.

The reverse current protection feature prevents current from flowing backward from the output to the input when the input voltage drops below the output voltage. This is important in battery-powered applications where the battery may be removed while the output capacitor is still charged, or in systems with multiple power sources where one source may backfeed through the LDO.

At $1.26 per unit in volume (1000+), the ADP1755ACPZ-R7 is priced competitively for a 1.2 A, high-PSRR, low-noise LDO with power-good and soft-start features. It offers a more complete feature set than simpler LDOs (e.g., TPS73701) at a similar or lower price point.

The ADP1755ACPZ-R7 operates as a CMOS low dropout linear regulator using a P-channel MOSFET pass transistor controlled by a high-gain error amplifier.

Pass Transistor: The ADP1755 uses a P-channel MOSFET as the pass element between VIN and VOUT. The PMOS transistor is driven by the error amplifier output, which adjusts the gate voltage to maintain the desired output voltage. The PMOS pass transistor has a very low on-resistance (approximately 88 mOhm), which results in the 105 mV dropout voltage at 1.2 A. When the input-output voltage differential is less than the dropout voltage, the PMOS transistor operates in the linear (ohmic) region and acts as a variable resistor controlled by the error amplifier.

Error Amplifier and Feedback: The error amplifier compares a fraction of the output voltage (from the ADJ pin) with the internal 0.5 V reference. The output of the error amplifier drives the gate of the PMOS pass transistor to minimize the difference between the feedback voltage and the reference. The feedback divider consists of two external resistors (R1 and R2) connected between VOUT, ADJ, and GND. The output voltage is VOUT = 0.5 V x (1 + R1/R2). The error amplifier has high DC gain (typically 60-80 dB) to achieve excellent load and line regulation.

Reference Voltage: The internal 0.5 V bandgap reference is trimmed at the factory to achieve plus or minus 1 percent initial accuracy. The reference is designed to be stable over temperature, contributing to the overall plus or minus 2 percent accuracy over line, load, and temperature.

Dropout Operation: When the input voltage drops to within the dropout voltage of the output voltage (VIN less than VOUT + 105 mV at 1.2 A), the PMOS pass transistor enters the ohmic (triode) region. In this region, the regulator can no longer maintain the desired output voltage because the pass transistor is fully enhanced (minimum RDS(on)). The output voltage tracks the input voltage minus the IR drop across the pass transistor. The dropout voltage is proportional to the load current: VDO = IOUT x RDS(on) = IOUT x 88 mOhm.

Soft Start: The soft start circuit limits the inrush current during power-up by controlling the ramp rate of the output voltage. An external capacitor on the SS pin is charged by an internal current source, and the SS pin voltage controls the reference voltage ramp. The output voltage follows the SS pin voltage until it reaches the regulation set point. The soft start time is approximately tSS = CSS x VREF / ISS, where ISS is the internal charging current. With no external capacitor, the internal default ramp provides a fast but controlled startup.

Power-Good: The power-good comparator monitors the feedback voltage (ADJ pin) and compares it to a threshold (approximately 90 percent of the 0.5 V reference). When the feedback voltage is above the threshold, the PG output is high-impedance (open-drain off). When the feedback voltage drops below the threshold (indicating the output is out of regulation), the PG output pulls LOW through an internal N-channel MOSFET. The PG output requires an external pull-up resistor (typically 10-100 kOhm) to a logic supply.

PSRR: The high PSRR is achieved through the combination of the high-gain error amplifier, the PMOS pass transistor (which provides inherent supply rejection), and the internal compensation network. The PSRR decreases with frequency as the error amplifier gain rolls off, from 65 dB at 1 kHz to 54 dB at 100 kHz. At higher frequencies (above 100 kHz), the output capacitor provides additional filtering.

Current Limit: The current limit circuit monitors the current through the PMOS pass transistor using a scaled sense transistor. When the output current exceeds the current limit threshold (1.5 A minimum, typically 2.0 A), the error amplifier reduces the gate drive to the pass transistor, limiting the output current. The current limit is a foldback type that reduces the current limit under short-circuit conditions to reduce power dissipation.

Thermal Protection: A thermal sensor on the die monitors the junction temperature. When the junction temperature exceeds approximately 150 degrees C, the thermal shutdown circuit turns off the pass transistor. When the junction temperature drops below approximately 130 degrees C, the LDO restarts with the soft start sequence. The thermal shutdown has approximately 20 degrees C of hysteresis to prevent oscillation.

Reverse Current Protection: The reverse current protection circuit monitors the input and output voltages. When VOUT is higher than VIN (e.g., when the input supply is removed while the output capacitor is still charged), an internal circuit turns off the body diode of the PMOS pass transistor, preventing current from flowing from VOUT to VIN. This eliminates the need for an external Schottky diode across the LDO for reverse current protection.