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AD5330BRUZ

8-bit parallel DAC with rail-to-rail output, 115µA supply current, 2.5-5.5V in TSSOP-20

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Manufacturer Part：

AD5330BRUZ

Package：

TSSOP-20 (6.50 x 4.40 x 0.90 mm) RU-20

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Description

Product Overview

The AD5330BRUZ from Analog Devices is an 8-bit voltage-output DAC with rail-to-rail output and parallel interface in a 20-lead TSSOP package. It operates from a single 2.5V to 5.5V supply, consuming only 115µA at 3V. The device features double-buffered input logic, power-on reset to 0V, and programmable output gain of 1x or 2x VREF.

Key Specifications

Resolution 8-bit
Output Voltage Range 0V ~ VREF or 0V ~ 2×VREF
Supply Voltage 2.5V ~ 5.5V
Interface Parallel (8-bit data bus)
Supply Current 115µA @ 3V, 140µA @ 5V
Power-Down Current 80nA @ 3V, 200nA @ 5V
Output Settling Time 6µs (to 1/2 LSB)
Package TSSOP-20 (6.5 x 4.4mm)
Operating Temperature -40°C ~ +85°C (B Grade)

Features

  • Rail-to-rail output with 1x or 2x gain selection
  • Ultra-low power: 115µA at 3V operating, 80nA power-down
  • Double-buffered parallel input logic
  • Power-on reset to 0V (zero-scale)
  • LDAC pin for simultaneous DAC update
  • Asynchronous CLR function resets to 0V
  • Buffered or unbuffered reference input option
  • Guaranteed monotonic by design

Applications

  • Portable battery-powered instruments
  • Digital gain and offset adjustment
  • Programmable voltage and current sources
  • Industrial process control
  • Programmable attenuators

The AD5330 is a single 8-bit digital-to-analog converter (DAC) that operates from a single 2.5V to 5.5V supply, consuming only 115µA at 3V. The device features an on-chip output buffer amplifier capable of generating rail-to-rail output voltages. The GAIN pin allows the output range to be set at 0V to VREF or 0V to 2×VREF. The parallel interface uses CS and WR signals to load data, while LDAC provides simultaneous update of the DAC output. The power-on reset circuit ensures the DAC output powers up at 0V.

The AD5330 uses a resistor-string DAC architecture followed by an output buffer amplifier. The 8-bit digital code selects a tap point on the resistor string, generating a voltage proportional to VREF. The output buffer provides low-impedance drive capability and rail-to-rail output swing. Input data is double-buffered: the first stage (input register) captures data on the rising edge of WR with CS low, and the LDAC signal transfers data from the input register to the DAC register, updating the output. This double-buffering allows multiple DACs in a system to be updated simultaneously.

Pin Name Function
1-8 DB7-DB0 Parallel data input bus (MSB to LSB)
9 CS Chip select (active low)
10 WR Write input (active low, rising edge latches data)
11 LDAC Load DAC register (active low)
12 GND Ground reference
13 VOUT DAC analog output voltage
14 VDD Positive power supply (2.5-5.5V)
15 VREF External reference voltage input
16 BUF Reference buffer enable (high=buffered)
17 GAIN Output gain select (low=1x, high=2x VREF)
18 CLR Asynchronous clear to 0V (active low)
19 PD Power-down enable (active high)
20 NC No connect
  • Battery-Powered Calibration: 115µA operating current and 80nA power-down suit long-life portable calibration instruments
  • Process Control Setpoint: Parallel interface allows fast update from 8-bit microcontroller bus for real-time setpoint adjustment
  • Programmable Bias Generator: 2x VREF gain mode extends output range while maintaining 8-bit resolution from a low-voltage reference
  • Multi-DAC System: LDAC pin enables synchronous update of multiple AD5330 devices for multi-channel control
Model Manufacturer Key Difference
AD5331BRUZ ADI 10-bit version, same package
AD5340BRUZ ADI 12-bit, 24-lead TSSOP
AD5341BRUZ ADI 12-bit, 20-lead TSSOP
DAC0800CM TI 8-bit, current output, DIP-16
MCP4921-E/SN Microchip 12-bit, SPI interface, 8-SOIC
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Address: Room 2919, Guoli Building, Huaqiang North, Futian District, Shenzhen, Guangdong, China
 

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