STM32F103RBT6

The STM32F103RBT6 from STMicroelectronics is a mainstream performance line ARM Cortex-M3 microcontroller that offers an excellent balance of processing power, peripheral integration, and cost-effectiveness in a 64-pin LQFP package. With 128 KB of Flash memory and 20 KB of SRAM, it provides sufficient resources for a wide range of embedded applications, from motor control to industrial communication.

The STM32F103RBT6 is part of the medium-density STM32F103xx family, which includes devices with 64 or 128 KB Flash in packages from 36 to 100 pins. The R suffix denotes a 64-pin package, the B suffix denotes 128 KB Flash, and the T6 suffix denotes LQFP package with -40C to +85C industrial temperature range. This positions the STM32F103RBT6 as a step up from the popular STM32F103C8T6 (48-pin LQFP, 64 KB Flash), offering more GPIO (51 vs 37), more Flash (128 KB vs 64 KB), and the addition of CAN and USB interfaces.

The ARM Cortex-M3 core delivers 1.25 DMIPS/MHz at 72 MHz, providing 90 DMIPS of processing power. While significantly less powerful than the Cortex-M4-based STM32F4 series (168 MHz, FPU, DSP), the Cortex-M3 is more than adequate for real-time control, communication protocol processing, and moderate computational workloads. The lack of a hardware FPU means floating-point operations are emulated in software, which is acceptable for many control applications but may be a bottleneck for heavy signal processing.

The dual 12-bit ADCs are a key strength, providing up to 16 external channels with 1 us conversion time. In dual ADC mode, the two ADCs can operate simultaneously, enabling synchronized sampling of multiple channels (e.g., sampling all three phases of a motor simultaneously). The internal temperature sensor provides die temperature monitoring for thermal management. The ADC supports DMA transfers, enabling continuous conversion without CPU intervention.

The motor control PWM timer (TIM1) provides six PWM channels with complementary output, dead-time insertion, and break input for emergency stop. This makes the STM32F103RBT6 suitable for 3-phase motor control applications including BLDC, PMSM, and AC induction motor drives. The quadrature encoder interface in the general-purpose timers simplifies connection to incremental encoders for position feedback.

The USB 2.0 full-speed device interface includes an on-chip PHY, requiring only an external 1.5 kOhm pull-up resistor on the DP line. The USB peripheral supports all standard USB device classes (CDC, HID, MSC, custom) and includes dedicated USB SRAM buffers. The CAN 2.0B interface supports both standard (11-bit) and extended (29-bit) identifiers with three transmit mailboxes, two receive FIFOs, and loop-back/silent modes for diagnostics.

The 7-channel DMA controller offloads data transfer tasks from the CPU, enabling high-throughput communication (SPI, I2C, USART), continuous ADC sampling, and memory-to-memory transfers without CPU intervention. Each DMA channel can be configured for peripheral-to-memory, memory-to-peripheral, or memory-to-memory transfers with configurable priority levels.

The LQFP-64 package exposes 51 of the possible 80 GPIO pins, providing a good balance between I/O availability and board space. The exposed pins include all of Port A (16 pins), Port B (16 pins), most of Port C (13 pins), and a few Port D pins. This is sufficient for most medium-complexity applications while keeping the PCB layout manageable.

The STM32F103RBT6 operates as a 32-bit ARM Cortex-M3 microcontroller with on-chip Flash, SRAM, and an extensive peripheral set connected through a multi-bus matrix.

ARM Cortex-M3 Core: The Cortex-M3 implements the ARMv7-M architecture with a 3-stage pipeline (fetch, decode, execute). It supports 56 base instructions plus additional DSP extensions including saturated arithmetic, multiply-accumulate (MAC), and hardware divide. The NVIC (Nested Vectored Interrupt Controller) supports up to 43 maskable interrupt channels plus the non-maskable interrupt (NMI), with 16 programmable priority levels. The interrupt latency is deterministic at 12 cycles (6 cycles tail-chaining). The processor includes a Memory Protection Unit (MPU) with 8 regions for privilege separation and memory access control.

Bus Matrix: The multi-AHB bus matrix connects the Cortex-M3 core, DMA controller, and peripherals through three AHB buses: I-bus (instruction fetch from Flash/SRAM), D-bus (data access from Flash/SRAM), and S-bus (system bus for peripheral register access). The DMA controller shares access to SRAM and peripherals through the bus matrix, enabling concurrent CPU and DMA operations when they access different targets. The AHB is clocked at up to 72 MHz, with the APB1 bus at up to 36 MHz and the APB2 bus at up to 72 MHz.

Flash Memory with Prefetch: The Flash memory has a native access time that requires wait states at 72 MHz (typically 2 wait states). The prefetch buffer (2 x 64-bit lines) fetches the next instruction ahead of the current execution, mitigating the wait-state penalty for linear code execution. Branches and random accesses still incur the full wait-state penalty.

Clock System: The clock tree provides flexible clock configuration. The System Clock (SYSCLK) can be sourced from HSI (8 MHz internal RC), HSE (4-16 MHz external crystal), or PLL. The PLL can multiply the HSE or HSE/2 to generate up to 72 MHz. The AHB prescaler divides SYSCLK for the AHB bus, and the APB1/APB2 prescalers further divide the AHB clock for the peripheral buses. The RTC can use LSE (32.768 kHz crystal) or LSI (40 kHz internal RC) for independent timekeeping.

ADC Dual Mode: The two ADCs can operate independently or in combined modes. In regular simultaneous mode, both ADCs convert different channels at the same time. In fast interleaved mode, both ADCs alternate conversions on the same channel to double the sampling rate. In slow interleaved mode, ADC1 and ADC2 alternate conversions with a delay for higher precision. The dual sample-and-hold circuits allow simultaneous sampling of two channels, which is essential for power metering and motor control where phase relationships must be preserved.

Motor Control Timer: TIM1 is an advanced-control timer specifically designed for motor drive applications. It provides up to 6 PWM outputs arranged as 3 complementary pairs (CH1/CH1N, CH2/CH2N, CH3/CH3N), with programmable dead-time insertion between complementary outputs to prevent shoot-through in half-bridge configurations. The break input (BKIN) provides emergency shutdown capability, immediately forcing all PWM outputs to a safe state. The repetition counter reduces the update event rate for slower control loops.

DMA Controller: The 7-channel DMA1 controller supports circular mode for continuous data acquisition (e.g., ADC samples streaming to SRAM), and normal mode for one-shot transfers. Each channel has configurable source and destination addresses, transfer width (byte/half-word/word), and transfer count. Interrupts on transfer complete, half-transfer, and transfer error allow the CPU to process data without polling.