RTL8197H-VE5-CG

The RTL8197H-VE5-CG is a highly integrated 2T2R 802.11b/g/n WiSoC (Wireless System-on-Chip) manufactured by Realtek Semiconductor Corp. It belongs to the RTL8197F family and is fabricated on a 28nm process node. The chip integrates a 1GHz MIPS 24Kc processor with 64KB I-Cache and 32KB D-Cache, a 2T2R 802.11b/g/n MAC/BB/RF wireless transceiver achieving up to 300Mbps PHY rate, a 5-port 10/100Mbps Fast Ethernet switch configurable as 5 FE PHY or 1 RGMII + 4 FE PHY, two USB 2.0 host controllers, 128MB of embedded DDR2 SDRAM (MCM package), and comprehensive peripheral interfaces including PCIe Gen1 Host, SPI, UART, I2C, I2S, PCM, SDXC/eMMC, and GPIO. The RTL8197H variant is differentiated from other RTL8197F series members by its 5-port FE switch supporting RGMII uplink for Gigabit Ethernet, making it ideal for multi-LAN port routers and mesh Wi-Fi nodes. A hardware Security Engine supports AES/DES/SHA cryptography, and a 4-channel GDMA controller offloads data transfer tasks. The chip supports Wi-Fi EasyMesh and is widely adopted in commercial products such as H3C NX15 (AX1500) and D-Link DIR-841 (AC1200).

1. Processor Subsystem: The MIPS 24Kc CPU runs at up to 1GHz with 64KB I-Cache and 32KB D-Cache, executing the embedded Linux kernel, network protocol stack (TCP/IP, NAT, firewall), and application-layer software through an internal AMBA bus fabric.
2. Wireless Subsystem: The 2.4GHz 2T2R 802.11b/g/n MAC/BB/RF transceiver is fully integrated on-chip, supporting HT20/HT40 channel bandwidths with MIMO processing for up to 300Mbps PHY rate. Integrated PA/LNA minimize external RF components. Transmit Beamforming (TxBF), STBC, LDPC-Tx, and MRC-Rx are supported for enhanced link reliability.
3. Ethernet Switch Subsystem: A 5-port 10/100Mbps Fast Ethernet switch supports configurable port mapping — either 5 FE PHY or 1 RGMII + 4 FE PHY mode. The RGMII MAC interface connects to an external Gigabit PHY (e.g., RTL8211F) for 1000M WAN/LAN, with Auto MDI/MDIX on all FE ports.
4. Memory Subsystem: 128MB DDR2 SDRAM is embedded within the MCM package. The memory controller supports SPI NOR Flash (up to 128MB), SPI NAND Flash (up to 4Gbit), and Parallel NAND Flash (up to 8GB) for firmware storage. Typical designs use 16MB SPI NOR Flash.
5. Peripheral Interface Subsystem: Rich I/O includes 1x PCIe Gen1 Host, 2x USB 2.0, 2x SPI, 3x UART, 2x I2C, 1x I2S, 1x PCM, 4x PWM, and 1x SDXC/eMMC for flexible IoT, VoIP, and storage expansion.
6. Hardware Acceleration Engine: A dedicated Security Engine supports AES/DES/SHA-1/SHA-256 hardware cryptography for VPN and WPA encryption offload. The GDMA controller provides 4 independent DMA channels for memory-to-memory and memory-to-peripheral transfers without CPU intervention.