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NC7WZ07P6X

Dual open-drain inverter w/ enable, 1.65-5.5V, 3ns, SC-88/SOT-363

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Manufacturer Part：

NC7WZ07P6X

Package：

SC-88 / SOT-363 (2.1 x 1.35 x 1.0 mm)

Description

Product Overview

The NC7WZ07P6X from onsemi (formerly Fairchild) is a dual unbuffered open-drain inverter with dual enable in a 6-pin SC-88 (SOT-363) package. Designed for 1.65V to 5.5V operation, it provides configurable open-drain logic functions with very low static power consumption.

Key Specifications

Logic Type	Dual Unbuffered Inverter, Open-Drain
Channels	2 (with individual enables)
Supply Voltage	1.65V to 5.5V
Propagation Delay	3.0 ns (typ @ 5V)
Output Drive	24 mA (Io)
Static Supply Current	1 uA (max)
Operating Temperature	-40 to +85 C
Package	SC-88 / SOT-363 (6-pin)

Features

Dual unbuffered open-drain inverter
Individual enable inputs per channel
1.65V to 5.5V supply range
3.0ns typical propagation delay at 5V
Open-drain outputs for wired-OR logic
Ultra-low 1uA static current
Pb-free, RoHS compliant

Applications

Wired-OR bus interfaces
Level translation
I2C/SMBus pull-down drivers
General-purpose open-drain logic

Product Introduction:NC7WZ07P6X Product Introduction

The NC7WZ07P6X from onsemi is a dual unbuffered open-drain inverter with individual enable inputs in a tiny 6-pin SC-88 (SOT-363) package. The open-drain outputs enable wired-OR logic connections, level translation between voltage domains, and I2C/SMBus pull-down driver applications. Operating from 1.65V to 5.5V with only 3ns propagation delay at 5V, it combines high speed with ultra-low 1uA static power consumption. The P6X suffix denotes the SC-88 package with tape and reel packaging.

Working Principle:NC7WZ07P6X Working Principle

The NC7WZ07 operates through three subsystems: (1) Open-Drain Inverter: Each channel inverts the input signal and presents it on an open-drain output. When the input is high, the output NMOS is off (high impedance). When the input is low, the output NMOS pulls to ground. External pull-up resistors determine the output high level. (2) Individual Enables: Each inverter has a dedicated enable input. When the enable is low, the output is forced to high impedance regardless of the input, allowing selective channel disabling. (3) Unbuffered Architecture: Direct CMOS inverter stages without additional buffering provide minimum propagation delay (3ns at 5V) for high-speed logic applications.

Pin Description:NC7WZ07P6X Pin Definition and Functions

Pin	Name	Type	Description
1	1OE	Input	Channel 1 output enable (active high)
2	1A	Input	Channel 1 input
3	2Y	Output	Channel 2 open-drain output
4	2A	Input	Channel 2 input
5	GND	Power	Ground
6	VCC	Power	Supply (1.65-5.5V)