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SN74LVC04ADR

Hex inverter, 1.65-3.6V, 5.5V inputs, 4.3ns, SOIC-14

18900

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Pieza del fabricante：

SN74LVC04ADR

Paquete：

14-Pin SOIC (8.65 x 3.91 x 1.27 mm)

Marca：
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Descripción

Productos

The SN74LVC04ADR is a Texas Instruments hex inverter (six independent inverters) designed for 1.65V to 3.6V VCC operation with 5.5V-tolerant inputs. It features 4.3ns max propagation delay at 3.3V and exceeds 250mA latch-up performance. Packaged in 14-pin SOIC, -40C to +125C.

Especificaciones

Función Hex inverter (6x)
VCC Range 1.65 V to 3.6 V
Input Voltage Up to 5.5 V
tpd (max) 4.3 ns at 3.3 V
Canales 6

Características

  • Six independent inverters
  • 1.65V to 3.6V VCC operation
  • 5.5V tolerant inputs
  • 4.3ns max propagation delay at 3.3V
  • 250mA latch-up performance
  • SOIC-14 package

Aplicaciones

  • Logic level inversion
  • Clock signal complementing
  • 5V-to-3.3V translation with inversion
  • General-purpose logic

The SN74LVC04ADR is a Texas Instruments hex inverter containing six independent inverters in a single 14-pin SOIC package. Each inverter performs the Boolean function Y = NOT A. The device operates from 1.65V to 3.6V VCC while inputs accept voltages up to 5.5V, enabling mixed-voltage systems where 5V logic signals are interfaced with 3.3V or lower-voltage logic. The 4.3ns maximum propagation delay at 3.3V supports high-speed digital operation. The Ioff feature supports partial-power-down mode and live insertion. Latch-up performance exceeds 250mA per JESD 17. This device is a fundamental building block for logic inversion, clock complementing, and active-low signal generation.

Each inverter in the SN74LVC04A is a single-stage CMOS inverter consisting of a PMOS pull-up transistor and an NMOS pull-down transistor. When the input is low, the PMOS turns on and the NMOS turns off, driving the output high. When the input is high, the PMOS turns off and the NMOS turns on, driving the output low. The input stage includes clamp diodes that allow input voltages up to 5.5V regardless of VCC, enabling the device to accept and invert 5V logic levels while operating from a 3.3V supply. The balanced CMOS output stage provides symmetric source and sink drive capability.

Pin Mnemonic Descripción
1,3,5,9,11,13 1A-6A Inputs
2,4,6,8,10,12 1Y-6Y Outputs (inverted)
7 GND Suelo
14 VCC Supply
  • Clock signal inversion for complementary clock generation in digital systems
  • Active-low enable generation from active-high control signals
  • 5V-to-3.3V logic level translation with inversion
  • General-purpose logic inversion in multi-voltage bus systems
Modelo Fabricante Diferencia clave
SN74LVC04APWR TI TSSOP-14 package
74LVC04APW NXP Compatible con clavijas
SN74LVC14ADR TI Hex inverter with Schmitt trigger
NC7SV04 onsemi Single inverter, tiny
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Address: Room 2919, Guoli Building, Huaqiang North, Futian District, Shenzhen, Guangdong, China
 

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