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SN74LS373N

Octal transparent latch, 3-state, LE/OE, PDIP-20

4800

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Pieza del fabricante：

SN74LS373N

Paquete：

PDIP-20 (24.33 x 6.35 x 5.08mm, 2.54mm pitch, through-hole)

Marca：

Categorías de productos：

Circuitos integrados IC, Circuitos integrados de interfaz

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Descripción

Productos

The SN74LS373N from Texas Instruments is an octal transparent D-type latch with 3-state outputs, controlled by a single latch enable and output enable, in a 20-pin PDIP package.

Especificaciones

Number of Latches	8 (octal)
Logic Family	LS (Low-power Schottky)
Tensión de alimentación	4.75V to 5.25V (5V nominal)
Latch Enable (LE)	Transparent when HIGH, latched when LOW
Output Enable (OE)	Active-low; HIGH = 3-state (high impedance)
Output Type	3-state (for bus sharing)
Retardo de propagación	18ns typical (D to Q, LE=HIGH)
Latch Hold Time	10ns minimum
Temperatura de funcionamiento	0°C to +70°C
Paquete	PDIP-20 (24.33 x 6.35mm)

Características

8-bit transparent D-type latch
3-state outputs for bus driving
Single latch enable for all 8 bits
Output enable for bus sharing
18ns typical propagation delay
Industry-standard 74373 pinout

Aplicaciones

Address latch for multiplexed bus
Output port expansion
Data capture and hold
Bus buffering and isolation
Microprocessor I/O latching

Introducción del producto:SN74LS373N Presentación del producto

The SN74LS373N from Texas Instruments is an octal transparent D-type latch with 3-state outputs, commonly used for address latching on multiplexed address/data buses such as the Intel 8051 microcontroller. When the latch enable (LE) is HIGH, the eight D inputs pass transparently to the Q outputs. When LE transitions from HIGH to LOW, the current data is latched (held) on the Q outputs, and further changes on D are ignored. The output enable (OE) is active-low; when OE is HIGH, all eight outputs are in the high-impedance state, effectively disconnecting the latch from the bus. When OE is LOW, the latched data appears on the outputs. The transparent mode (LE=HIGH) allows the latch to function as a buffer, while the latched mode (LE=LOW) holds data for downstream circuitry. The 3-state outputs allow multiple 373s to share a common bus. The N suffix denotes the PDIP-20 through-hole package.

Principio de funcionamiento:SN74LS373N Principio de funcionamiento

The SN74LS373N contains eight identical D-type latches. When the latch enable (LE) is HIGH, each latch is transparent: the Q output follows the D input. When LE goes LOW, each latch captures the D input value present at the LE transition and holds it. While LE is LOW, changes on D do not affect Q. This transparent-then-latch behavior is essential for multiplexed bus systems: the address and data share the same physical bus lines, and the 373 captures the address during the address phase of the bus cycle so that the address remains stable while the data phase uses the same bus lines. The output enable (OE) controls the 3-state output buffers: when OE is LOW, the latched Q values drive the output pins; when OE is HIGH, the outputs are high-impedance (floating), allowing other devices to drive the bus. The 10ns latch hold time means the D input must be stable for at least 10ns after LE goes LOW for reliable latching. In an 8051 system, the ALE (Address Latch Enable) signal connects to LE; ALE goes HIGH during the address phase (allowing address to pass through to the latch) and goes LOW to latch the address before the data phase begins.

Descripción de la clavija:SN74LS373N Definición y funciones de las clavijas

Pin	Nombre	Tipo	Descripción
1	OE	Entrada	Output enable (active LOW; HIGH=3-state)
2	1Q	Salida	Latch 1 output (3-state)
3	1D	Entrada	Latch 1 data input
4	2D	Entrada	Latch 2 data input
5	2Q	Salida	Latch 2 output (3-state)
6	3Q	Salida	Latch 3 output (3-state)
7	3D	Entrada	Latch 3 data input
8	4D	Entrada	Latch 4 data input
9	4Q	Salida	Latch 4 output (3-state)
10	GND	Potencia	Suelo
11	LE	Entrada	Latch enable (HIGH=transparent, LOW=latched)
12	5Q	Salida	Latch 5 output (3-state)
13	5D	Entrada	Latch 5 data input
14	6D	Entrada	Latch 6 data input
15	6Q	Salida	Latch 6 output (3-state)
16	7Q	Salida	Latch 7 output (3-state)
17	7D	Entrada	Latch 7 data input
18	8D	Entrada	Latch 8 data input
19	8Q	Salida	Latch 8 output (3-state)
20	VCC	Potencia	Supply (4.75V to 5.25V)

Application Scenarios:In which products and applications isSN74LS373N usado

8051 Address Latch: AD0-AD7 → D0-D7; ALE → LE; Q0-Q7 → address bus; latches address when ALE falls
Output Port: D from data bus; LE from /WR + /CS; OE always LOW; latched outputs drive peripherals
Input Capture: External data → D; LE from control signal; captures snapshot of 8-bit data on LE falling edge
Bus Isolation: OE controlled by system; disconnects latch from bus when not addressed; multiple 373s share one bus
Pipeline Stage: LE from system clock; captures data on one phase, holds for next; 8-bit pipeline register

Alternative Models:What chips are recommended as replacements for SN74LS373N

Modelo	Fabricante	Diferencia clave	Paquete	Supply
74LS373N	TI/Nexperia	Original TTL version with 5V-only supply, typical propagation delay 10-15ns	DIP-20	5V TTL
74LS373D	TI/Nexperia	Surface-mount SOIC version of LS with identical logic function	SOIC-20	5V TTL
74HC373D	TI/Nexperia	CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity	SOIC-20	2-6V CMOS
74HC373N	TI/Nexperia	Through-hole DIP version of HC family for prototyping and repair	DIP-20	2-6V CMOS
74HCT373D	TI/Nexperia	CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V	SOIC-20	4.5-5.5V TTL-in
74HCT373N	TI/Nexperia	Through-hole DIP version of HCT family for prototyping and repair	DIP-20	4.5-5.5V TTL-in
74LVC373D	TI/Nexperia	Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs	SOIC-20	1.65-3.6V CMOS
74LVC373N	TI/Nexperia	Through-hole DIP version of LVC family for prototyping and repair	DIP-20	1.65-3.6V CMOS

The 74373 is a Octal Transparent Latch with 3-State Output. Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.