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SN74LS192N

4-bit BCD up/down counter, separate clocks, async load/clear, carry/borrow, LS TTL, PDIP-16

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Pieza del fabricante：

SN74LS192N

Paquete：

PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

Marca：

Categorías de productos：

Circuitos integrados IC, Circuitos integrados de interfaz

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Descripción

Productos

The SN74LS192N from Texas Instruments is a synchronous 4-bit BCD up/down counter with separate up and down clock inputs, asynchronous clear, and parallel load — the most versatile BCD counter in the LS family in a 16-pin PDIP package.

Especificaciones

Función	Synchronous 4-bit BCD up/down counter
Logic Family	LS (Low-power Schottky)
Tensión de alimentación	4.75V to 5.25V
Count Range	0-9 (BCD decade)
Clock Inputs	UP (count up), DOWN (count down), separate, negative-edge
Parallel Load	Asynchronous, active-LOW (LOAD)
Clear	Asynchronous, active-HIGH (CLR)
Carry/Borrow	CO (carry out, active-LOW), BO (borrow out, active-LOW)
Max Clock Frequency	25MHz typical
Temperatura de funcionamiento	0°C to +70°C
Paquete	PDIP-16 (19.3 x 6.35mm)

Características

Separate UP and DOWN clock inputs
Synchronous counting in both directions
Asynchronous parallel load (preset any BCD value)
Asynchronous clear (CLR, active-HIGH)
Carry and borrow outputs for cascading
BCD count sequence: 0-9 up, 9-0 down

Aplicaciones

Up/down decade counters
Digital position encoders
Score counters
Frequency synthesizers

Introducción del producto:SN74LS192N Presentación del producto

The SN74LS192N from Texas Instruments is a synchronous 4-bit BCD up/down counter with separate UP and DOWN clock inputs. This dual-clock design means the counter direction is determined by which clock input receives pulses: pulses on UP count 0→1→2→…→9→0; pulses on DOWN count 9→8→7→…→0→9. The unused clock input must be held HIGH during counting. The 74192 is the most feature-rich BCD counter: it has asynchronous parallel load (LOAD=LOW loads D0-D3 into the counter regardless of clocks), asynchronous clear (CLR=HIGH resets to 0), and carry/borrow outputs for cascading. CO goes LOW when counting UP and the count reaches 9 (carry to next stage); BO goes LOW when counting DOWN and the count reaches 0 (borrow from next stage). For cascading: CO → UP of next stage; BO → DOWN of next stage. The 74193 is the binary (0-15) version with identical pinout. The N suffix denotes the PDIP-16 package.

Principio de funcionamiento:SN74LS192N Principio de funcionamiento

The SN74LS192N counts in BCD (0-9) on the negative edge of either the UP or DOWN clock. Counting UP: pulses on UP, DOWN must be HIGH. Sequence: 0→1→2→3→4→5→6→7→8→9→0 (carry). At 9, CO goes LOW on the next UP clock (carry to next decade). Counting DOWN: pulses on DOWN, UP must be HIGH. Sequence: 9→8→7→6→5→4→3→2→1→0→9 (borrow). At 0, BO goes LOW on the next DOWN clock (borrow from next decade). Parallel load: LOAD=LOW loads D0-D3 into the counter asynchronously (overrides clocks and counting). CLR=HIGH resets Q0-Q3 to 0 asynchronously (overrides LOAD, clocks). Priority: CLR > LOAD > clocks. For multi-decade counting: CO of units → UP of tens; BO of units → DOWN of tens; both clock inputs of tens are independently driven by the carry/borrow of the units stage. The 74192 counts in BCD; the 74193 (same pinout) counts in binary (0-15). Both share the same dual-clock, load, clear, carry/borrow architecture.

Descripción de la clavija:SN74LS192N Definición y funciones de las clavijas

Pin	Nombre	Tipo	Descripción
1	DOWN	Entrada	Count-down clock (negative edge, UP must be HIGH)
2	Q1	Salida	Output bit 1
3	Q0	Salida	Output bit 0 (LSB)
4	BO	Salida	Borrow output (active-LOW; LOW at count=0 with DOWN clock)
5	CO	Salida	Carry output (active-LOW; LOW at count=9 with UP clock)
6	Q3	Salida	Output bit 3 (MSB)
7	Q2	Salida	Output bit 2
8	GND	Potencia	Suelo
9	D2	Entrada	Parallel data input bit 2
10	D3	Entrada	Parallel data input bit 3 (MSB)
11	D0	Entrada	Parallel data input bit 0 (LSB)
12	D1	Entrada	Parallel data input bit 1
13	LOAD	Entrada	Parallel load enable (active-LOW, loads D0-D3)
14	CLR	Entrada	Asynchronous clear (active-HIGH, resets to 0)
15	UP	Entrada	Count-up clock (negative edge, DOWN must be HIGH)
16	VCC	Potencia	Supply (5V)

Application Scenarios:In which products and applications isSN74LS192N usado

2-Digit Score Counter: Two 74192s; units CO → tens UP; units BO → tens DOWN; UP button increments; DOWN button decrements; score 00-99
Presettable Counter: D0-D3 set to desired start value; pulse LOAD; counter starts from preset value; count up or down from preset
Position Encoder: Rotary encoder generates UP/DOWN pulses; 74192 tracks position (0-9); display on 7-segment via CD4511
Frequency Synthesizer: Thumbwheel switches → D0-D3; LOAD presets divider ratio; counter counts down to 0; BO reloads preset; programmable divider

Alternative Models:What chips are recommended as replacements for SN74LS192N

Modelo	Fabricante	Diferencia clave	Paquete	Supply
74LS192N	TI/Nexperia	Original TTL version with 5V-only supply, typical propagation delay 10-15ns	DIP-16	5V TTL
74LS192D	TI/Nexperia	Surface-mount SOIC version of LS with identical logic function	SOIC-16	5V TTL
74HC192D	TI/Nexperia	CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity	SOIC-16	2-6V CMOS
74HC192N	TI/Nexperia	Through-hole DIP version of HC family for prototyping and repair	DIP-16	2-6V CMOS
74HCT192D	TI/Nexperia	CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V	SOIC-16	4.5-5.5V TTL-in
74HCT192N	TI/Nexperia	Through-hole DIP version of HCT family for prototyping and repair	DIP-16	4.5-5.5V TTL-in

The 74192 is a 4-Bit Decade Counter (BCD, Up/Down). Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.