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SN74LS173N

4-bit D register, 3-state, dual data/output enable, async clear, LS TTL, PDIP-16

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Pieza del fabricante：

SN74LS173N

Paquete：

PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

Marca：

Categorías de productos：

Circuitos integrados IC, Circuitos integrados de interfaz

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Descripción

Productos

The SN74LS173N from Texas Instruments is a 4-bit D-type register with 3-state outputs and dual input/output enable controls — the TTL equivalent of the CD4076 for bus-oriented register applications in a 16-pin PDIP package.

Especificaciones

Función	4-bit D-type register with 3-state outputs
Logic Family	LS (Low-power Schottky)
Tensión de alimentación	4.75V to 5.25V
Register Bits	4
Reloj	Positive edge triggered
Data Enable	G1̄, G2̄ (both LOW = data enabled; any HIGH = register holds)
Output Enable	OE1̄, OE2̄ (both LOW = outputs active; any HIGH = high-Z)
Clear	Asynchronous, active-HIGH (CLR)
Retardo de propagación	20-30ns typical
Temperatura de funcionamiento	0°C to +70°C
Paquete	PDIP-16 (19.3 x 6.35mm)

Características

4-bit edge-triggered D register
3-state outputs for bus connection
Dual data enable (G1̄, G2̄) — hold when disabled
Dual output enable (OE1̄, OE2̄) — high-Z when disabled
Asynchronous clear

Aplicaciones

Bus registers in microprocessor systems
I/O port registers
Multi-master bus isolation
Data buffering

Introducción del producto:SN74LS173N Presentación del producto

The SN74LS173N from Texas Instruments is a 4-bit positive-edge-triggered D register with 3-state outputs and separate input/output enable controls. It captures 4 bits of data on the rising clock edge and holds them until the next qualified clock. The data enable inputs (G1̄, G2̄, both active-LOW) control whether new data is loaded: when both are LOW, D0-D3 are loaded on the next rising CLK edge; when either is HIGH, the register holds its current value (ignoring D inputs and clock). This is different from the CD4076 which forces inputs to zero when disabled — the 74173 holds its value instead, which is usually more useful. The output enable inputs (OE1̄, OE2̄, both active-LOW) control the 3-state outputs: when both are LOW, Q0-Q3 drive the bus; when either is HIGH, Q0-Q3 go to high-impedance. The asynchronous clear (CLR=HIGH) resets all bits to 0. The 74173 is the standard TTL bus register for microprocessor systems where multiple registers share a common data bus. The N suffix denotes the PDIP-16 package.

Principio de funcionamiento:SN74LS173N Principio de funcionamiento

The SN74LS173N captures data on the rising edge of CLK, subject to the data enable inputs. When both G1̄ and G2̄ are LOW (data enabled): on the rising CLK edge, D0-D3 are stored in the flip-flops and appear on Q0-Q3 (if outputs are enabled). When either G1̄ or G2̄ is HIGH (data disabled): the register holds its current value on the next clock edge; D inputs are ignored. This ‘hold’ behavior is achieved by feeding the current Q output back to the D input when the enable is inactive. Output control: when both OE1̄ and OE2̄ are LOW, Q0-Q3 drive the bus (active). When either OE1̄ or OE2̄ is HIGH, Q0-Q3 go to high-impedance (disconnected). For multi-register bus systems: a 2-to-4 decoder drives the OE inputs of four 74173 registers; only one register’s outputs are enabled at a time; the selected register drives the shared bus. Clear: CLR=HIGH asynchronously resets all bits to 0, overriding clock and data inputs. Data enable can be used as a clock enable: tie G1̄ to an enable signal; G2̄ to LOW; the register only loads new data when the enable is active.

Descripción de la clavija:SN74LS173N Definición y funciones de las clavijas

Pin	Nombre	Tipo	Descripción
1	OE1̄	Entrada	Output enable 1 (active-LOW; HIGH = high-Z)
2	Q0	Salida	Register output bit 0 (3-state)
3	Q1	Salida	Register output bit 1 (3-state)
4	Q2	Salida	Register output bit 2 (3-state)
5	Q3	Salida	Register output bit 3 (3-state)
6	GND	Potencia	Suelo
7	OE2̄	Entrada	Output enable 2 (active-LOW; HIGH = high-Z)
8	G2̄	Entrada	Data enable 2 (active-LOW; HIGH = hold)
9	G1̄	Entrada	Data enable 1 (active-LOW; HIGH = hold)
10	D3	Entrada	Register data input bit 3
11	D2	Entrada	Register data input bit 2
12	D1	Entrada	Register data input bit 1
13	D0	Entrada	Register data input bit 0
14	CLR	Entrada	Asynchronous clear (active-HIGH)
15	CLK	Entrada	Clock (positive edge)
16	VCC	Potencia	Supply (5V)

Application Scenarios:In which products and applications isSN74LS173N usado

Multi-Register Bus: Four 74173s share output bus; 2-to-4 decoder drives OE inputs; each register captures data from same input bus at different times; selected register drives output bus
Clock-Enabled Register: G1̄ = clock enable; G2̄ = LOW; register loads data only when enable active; holds when enable inactive
Output Port: MCU data bus → D0-D3; MCU write strobe → CLK; MCU address decode → OE1̄; register holds output data; drives peripheral bus
Input Port: Peripheral data → D0-D3; MCU read strobe → CLK (via address decode); OE enables bus drive; register buffers input to MCU bus

Alternative Models:What chips are recommended as replacements for SN74LS173N

Modelo	Fabricante	Diferencia clave	Paquete	Supply
74LS173N	TI/Nexperia	Original TTL version with 5V-only supply, typical propagation delay 10-15ns	DIP-16	5V TTL
74LS173D	TI/Nexperia	Surface-mount SOIC version of LS with identical logic function	SOIC-16	5V TTL
74HC173D	TI/Nexperia	CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity	SOIC-16	2-6V CMOS
74HC173N	TI/Nexperia	Through-hole DIP version of HC family for prototyping and repair	DIP-16	2-6V CMOS
74HCT173D	TI/Nexperia	CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V	SOIC-16	4.5-5.5V TTL-in
74HCT173N	TI/Nexperia	Through-hole DIP version of HCT family for prototyping and repair	DIP-16	4.5-5.5V TTL-in

The 74173 is a 4-Bit D-Type Register with 3-State Output. Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.