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SN74LS164N

8-bit serial-in parallel-out shift register, LS TTL, PDIP-14

5000

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Pieza del fabricante：

SN74LS164N

Paquete：

PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

Marca：

Categorías de productos：

Circuitos integrados IC, Circuitos integrados de interfaz

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Descripción

Productos

The SN74LS164N from Texas Instruments is an 8-bit serial-in parallel-out shift register — the TTL equivalent of the CD4094, ideal for expanding microcontroller outputs from 2 pins to 8 in a 14-pin PDIP package.

Especificaciones

Función	8-bit serial-in parallel-out shift register
Logic Family	LS (Low-power Schottky)
Tensión de alimentación	4.75V to 5.25V
Serial Inputs	A and B (both must be HIGH to shift in 1)
Outputs	Q0-Q7 (8 parallel outputs)
Clear	Asynchronous, active-LOW (CLR)
Trigger	Positive edge on CLK
Max Clock Frequency	25MHz typical
Temperatura de funcionamiento	0°C to +70°C
Paquete	PDIP-14 (19.3 x 6.35mm)

Características

8-bit serial-to-parallel conversion
Gated serial inputs (A AND B both HIGH = shift in 1)
Asynchronous clear (CLR, active-LOW)
Cascadable (Q7 → next A input)
25MHz clock rate

Aplicaciones

GPIO expansion (2 pins → 8 outputs)
LED chaser / display driver
Serial-to-parallel data conversion
Multi-chip display multiplexing

Introducción del producto:SN74LS164N Presentación del producto

The SN74LS164N from Texas Instruments is an 8-bit serial-in parallel-out shift register. Data is shifted in serially through the A and B gated inputs on each rising clock edge, and appears as 8 parallel outputs (Q0-Q7) after 8 clock cycles. The two serial inputs (A and B) are ANDed internally: a 1 is shifted in only when both A AND B are HIGH. This gating feature allows one input to serve as an active-HIGH enable while the other carries data — if either is LOW, a 0 is shifted in. The asynchronous clear (CLR=LOW) immediately resets all outputs to 0. For cascading, Q7 of one 74164 connects to the A input of the next; 2 chips give 16 outputs from 2 MCU pins (DATA + CLK). Unlike the 74HC595 which has an output latch and 3-state outputs, the 74164’s outputs update immediately as data shifts through — each output toggles as the shift register fills, which can cause flicker in display applications. The 74164 is simpler and cheaper than the 595, making it ideal for LED chasers and non-critical output expansion. The N suffix denotes the PDIP-14 through-hole package.

Principio de funcionamiento:SN74LS164N Principio de funcionamiento

The SN74LS164N shifts data on each rising clock edge. The data shifted in is the AND of inputs A and B: if both are HIGH, a 1 enters; if either is LOW, a 0 enters. On each rising CLK edge: Q0 takes the value of (A AND B); Q1 takes the old value of Q0; Q2 takes old Q1; … Q7 takes old Q6. After 8 clock cycles, 8 bits of serial data have been converted to 8 parallel outputs. The clear input (CLR=LOW) asynchronously forces all Q0-Q7 to 0 regardless of CLK. For normal operation, CLR must be HIGH. The gated inputs allow: A=data, B=enable (or vice versa); data is shifted in only when enable is HIGH; when enable is LOW, zeros are shifted in regardless of A. For cascading: Q7 → A of next 74164; B of all chips tied HIGH; shared CLK; shared CLR; 2 chips = 16 outputs, 3 chips = 24 outputs, all from 2 MCU pins. Unlike the 74HC595, the 74164 has no output latch: outputs change as data shifts through, so LED displays may flicker during shifting. For static displays, use the 74HC595 instead.

Descripción de la clavija:SN74LS164N Definición y funciones de las clavijas

Pin	Nombre	Tipo	Descripción
1	A	Entrada	Serial input A (gated with B)
2	B	Entrada	Serial input B (gated with A)
3	Q0	Salida	Parallel output bit 0 (first shift stage)
4	Q1	Salida	Parallel output bit 1
5	Q2	Salida	Parallel output bit 2
6	Q3	Salida	Parallel output bit 3
7	GND	Potencia	Suelo
8	CLK	Entrada	Clock (positive edge)
9	CLR	Entrada	Clear (active LOW, resets all outputs to 0)
10	Q4	Salida	Parallel output bit 4
11	Q5	Salida	Parallel output bit 5
12	Q6	Salida	Parallel output bit 6
13	Q7	Salida	Parallel output bit 7 (last stage, for cascading)
14	VCC	Potencia	Supply (5V)

Application Scenarios:In which products and applications isSN74LS164N usado

LED Chaser: MCU: DATA → A; CLK → CLK; CLR → HIGH; shift pattern: 10000000 → 01000000 → 00100000 → etc.; Q0-Q7 drive 8 LEDs; chasing effect
16-Output Expansion: Two 74164s; Q7(#1) → A(#2); shared CLK, B=HIGH, CLR=HIGH; 16 outputs from 2 MCU pins
7-Segment Multiplex: 74164 shifts segment data; common anode displays driven sequentially; one digit at a time
Gated Input: A=serial data, B=enable; shift in data only when B=HIGH; shift in zeros when B=LOW; selective data entry

Alternative Models:What chips are recommended as replacements for SN74LS164N

Modelo	Fabricante	Diferencia clave	Paquete	Supply
74LS164N	TI/Nexperia	Original TTL version with 5V-only supply, typical propagation delay 10-15ns	DIP-14	5V TTL
74LS164D	TI/Nexperia	Surface-mount SOIC version of LS with identical logic function	SOIC-14	5V TTL
74HC164D	TI/Nexperia	CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity	SOIC-14	2-6V CMOS
74HC164N	TI/Nexperia	Through-hole DIP version of HC family for prototyping and repair	DIP-14	2-6V CMOS
74HCT164D	TI/Nexperia	CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V	SOIC-14	4.5-5.5V TTL-in
74HCT164N	TI/Nexperia	Through-hole DIP version of HCT family for prototyping and repair	DIP-14	4.5-5.5V TTL-in

The 74164 is a 8-Bit Parallel-Out Serial Shift Register. Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.