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SN74LS157N

Quad 2:1 data selector MUX, single select, strobe, LS TTL, PDIP-16

4000

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Pieza del fabricante：

SN74LS157N

Paquete：

PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

Marca：

Categorías de productos：

Circuitos integrados IC, Circuitos integrados de interfaz

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Descripción

Productos

The SN74LS157N from Texas Instruments is a quad 2:1 data selector/multiplexer that chooses between two 4-bit data sources under a single select line — the standard digital 2:1 MUX in a 16-pin PDIP package.

Especificaciones

Función	Quad 2:1 data selector/multiplexer
Logic Family	LS (Low-power Schottky)
Tensión de alimentación	4.75V to 5.25V
Canales	4 (independent 2:1 selectors)
Data Inputs	1A,2A,3A,4A and 1B,2B,3B,4B
Select	A/B (single select; LOW=A, HIGH=B)
Strobe	G (active-LOW enable; LOW=active, HIGH=all outputs LOW)
Retardo de propagación	10-18ns typical
Temperatura de funcionamiento	0°C to +70°C
Paquete	PDIP-16 (19.3 x 6.35mm)

Características

Four 2:1 multiplexer channels with common select
Single A/B select input (LOW=A, HIGH=B)
Strobe (G) forces all outputs LOW when HIGH
Non-inverting data path
True output (not complemented)

Aplicaciones

4-bit data source selection
Parallel data switching
ALU input selection
Bus multiplexing

Introducción del producto:SN74LS157N Presentación del producto

The SN74LS157N from Texas Instruments is a quad 2:1 data selector/multiplexer that selects one of two 4-bit data sources based on a single select input. When A/B=LOW, outputs Y1-Y4 = A1-A4; when A/B=HIGH, outputs Y1-Y4 = B1-B4. The strobe input (G, active-LOW) enables the outputs: G=LOW = normal selection; G=HIGH = all outputs forced LOW regardless of data. The 74157 is the non-inverting version; the 74158 is the inverting version (outputs = complement of selected data). The single select line controls all four channels simultaneously, making the 74157 ideal for switching between two 4-bit data buses — a common need in ALU input selection, memory addressing, and parallel data routing. The 74157 is simpler than the CD4019 (which has two select inputs for AND-OR logic) — the 74157 provides straightforward 2:1 selection. The N suffix denotes the PDIP-16 package.

Principio de funcionamiento:SN74LS157N Principio de funcionamiento

The SN74LS157N selects between two 4-bit sources under a single A/B select control. Each of the four channels implements Yi = Ḡ · [(A/B̄)·Ai + (A/B)·Bi]. When G=LOW (enabled) and A/B=LOW: Yi = Ai (source A selected). When G=LOW and A/B=HIGH: Yi = Bi (source B selected). When G=HIGH (disabled): Yi = 0 (all outputs LOW, regardless of A/B, Ai, Bi). The non-inverting outputs mean Yi equals the selected data directly. For bus selection: two 4-bit buses connect to A and B inputs; A/B select chooses which bus drives the output; the selected bus data appears on Y1-Y4. For ALU input selection: two operand registers connect to A and B; A/B selects which operand feeds the ALU. The 74158 is the same but inverting: Yi = complement of selected data — useful when the next stage expects active-LOW inputs.

Descripción de la clavija:SN74LS157N Definición y funciones de las clavijas

Pin	Nombre	Tipo	Descripción
1	A/B	Entrada	Select input (LOW=A, HIGH=B)
2	1A	Entrada	Channel 1 data input A
3	1B	Entrada	Channel 1 data input B
4	1Y	Salida	Channel 1 output
5	2A	Entrada	Channel 2 data input A
6	2B	Entrada	Channel 2 data input B
7	2Y	Salida	Channel 2 output
8	GND	Potencia	Suelo
9	3Y	Salida	Channel 3 output
10	3B	Entrada	Channel 3 data input B
11	3A	Entrada	Channel 3 data input A
12	4Y	Salida	Channel 4 output
13	4B	Entrada	Channel 4 data input B
14	4A	Entrada	Channel 4 data input A
15	G	Entrada	Strobe (active-LOW enable; HIGH = all outputs LOW)
16	VCC	Potencia	Supply (5V)

Application Scenarios:In which products and applications isSN74LS157N usado

4-Bit Bus Select: Two 4-bit registers → A and B inputs; A/B selects which register drives the bus; Y1-Y4 = selected bus data
ALU Input Select: Two operand sets → A and B; A/B = operand select; Y1-Y4 → ALU inputs; select which operand to process
Memory Address Mux: PC → A inputs; MAR → B inputs; A/B = address source; Y1-Y4 = address to memory; PC or MAR selected
Parallel-to-Serial: Two 4-bit words → A and B; A/B alternates at 2× data rate; Y1-Y4 = time-multiplexed output; combined with shift register for serialization

Alternative Models:What chips are recommended as replacements for SN74LS157N

Modelo	Fabricante	Diferencia clave	Paquete	Supply
74LS157N	TI/Nexperia	Original TTL version with 5V-only supply, typical propagation delay 10-15ns	DIP-16	5V TTL
74LS157D	TI/Nexperia	Surface-mount SOIC version of LS with identical logic function	SOIC-16	5V TTL
74HC157D	TI/Nexperia	CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity	SOIC-16	2-6V CMOS
74HC157N	TI/Nexperia	Through-hole DIP version of HC family for prototyping and repair	DIP-16	2-6V CMOS
74HCT157D	TI/Nexperia	CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V	SOIC-16	4.5-5.5V TTL-in
74HCT157N	TI/Nexperia	Through-hole DIP version of HCT family for prototyping and repair	DIP-16	4.5-5.5V TTL-in
74AC157D	TI/Nexperia	Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC)	SOIC-16	2-6V CMOS
74AC157N	TI/Nexperia	Through-hole DIP version of AC family for prototyping and repair	DIP-16	2-6V CMOS
74LVC157D	TI/Nexperia	Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs	SOIC-16	1.65-3.6V CMOS
74LVC157N	TI/Nexperia	Through-hole DIP version of LVC family for prototyping and repair	DIP-16	1.65-3.6V CMOS

The 74157 is a Quad 2-Line to 1-Line Data Selector/Multiplexer. Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.