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SN74LS148N

8-to-3 priority encoder, active-LOW, cascade pins, LS TTL, PDIP-16

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Pieza del fabricante：

SN74LS148N

Paquete：

PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

Marca：

Categorías de productos：

Circuitos integrados IC, Circuitos integrados de interfaz

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Descripción

Productos

The SN74LS148N from Texas Instruments is an 8-line to 3-line priority encoder that accepts 8 active-LOW inputs and produces a 3-bit binary output representing the highest-priority active input in a 16-pin PDIP package.

Especificaciones

Función	8-line to 3-line priority encoder
Logic Family	LS (Low-power Schottky)
Tensión de alimentación	4.75V to 5.25V
Inputs	0-7 (active LOW, priority 7=highest)
Outputs	A2, A1, A0 (active LOW, binary of highest input)
Enable Input	EI (active LOW, enables encoder)
Group Outputs	GS (group signal, active LOW), EO (enable out, active LOW)
Retardo de propagación	10-15ns typical
Temperatura de funcionamiento	0°C to +70°C
Paquete	PDIP-16 (19.3 x 6.35mm)

Características

Priority encoding: highest-numbered active input wins
Cascading via EI, EO, and GS
Active-LOW inputs and outputs
GS output indicates any input is active
EO output indicates no input is active (for cascading)

Aplicaciones

Keyboard encoding
Interrupt priority encoding
Microprocessor interrupt controllers
Data input selection

Introducción del producto:SN74LS148N Presentación del producto

The SN74LS148N from Texas Instruments is an 8-line to 3-line priority encoder with active-LOW inputs and outputs. It accepts 8 input lines (0-7) and outputs a 3-bit binary code representing the highest-priority (highest-numbered) active input. Input 7 has the highest priority; input 0 has the lowest. If multiple inputs are active simultaneously, only the highest-priority input is encoded. The EI (enable input, active-LOW) must be LOW for the encoder to operate. The GS (group signal) output goes LOW when any input is active, providing a valid-data indicator. The EO (enable output) goes LOW only when no input is active (all inputs HIGH), enabling a lower-priority encoder in a cascaded system. Two 74148 encoders can be cascaded to form a 16-to-4 priority encoder: the higher-priority encoder’s EO connects to the lower-priority encoder’s EI; the A2-A0 outputs are ORed; and the GS outputs indicate which encoder is active. The N suffix denotes the PDIP-16 through-hole package.

Principio de funcionamiento:SN74LS148N Principio de funcionamiento

The SN74LS148N operates as a priority encoder. When EI=LOW (enabled): The encoder examines inputs 7 through 0 and finds the highest-numbered active (LOW) input. It outputs the 3-bit complement of that input number on A2, A1, A0. For example, if input 5 is the highest active input, A2,A1,A0 = 010 (complement of 5=101). GS goes LOW (indicating at least one input is active). EO stays HIGH (since there IS an active input). If no input is active (all HIGH): A2,A1,A0 = 111 (complement of 0, but meaningless); GS stays HIGH (no active input); EO goes LOW (indicating no active input, enabling next lower encoder). When EI=HIGH (disabled): All outputs go HIGH regardless of inputs. For 16-to-4 encoding: Higher-priority encoder (inputs 8-15): EI grounded. Its EO → EI of lower-priority encoder (inputs 0-7). Output bits: A2,A1,A0 of both encoders are NAND-gated; the higher-priority encoder’s GS provides the MSB (A3) of the 4-bit output.

Descripción de la clavija:SN74LS148N Definición y funciones de las clavijas

Pin	Nombre	Tipo	Descripción
1	A2	Salida	Encoded output MSB (active LOW)
2	EO	Salida	Enable output (active LOW; LOW = no input active)
3	GS	Salida	Group signal (active LOW; LOW = at least one input active)
4	A1	Salida	Encoded output bit 1 (active LOW)
5	A0	Salida	Encoded output LSB (active LOW)
6	7	Entrada	Input 7 (highest priority, active LOW)
7	6	Entrada	Input 6
8	GND	Potencia	Suelo
9	5	Entrada	Input 5
10	4	Entrada	Input 4
11	3	Entrada	Input 3
12	2	Entrada	Input 2
13	1	Entrada	Input 1
14	0	Entrada	Input 0 (lowest priority, active LOW)
15	EI	Entrada	Enable input (active LOW; LOW = enabled)
16	VCC	Potencia	Supply (5V)

Application Scenarios:In which products and applications isSN74LS148N usado

Interrupt Priority Encoder: 8 interrupt sources → inputs 0-7; A2-A0 → MCU interrupt vector; GS → MCU interrupt pin; highest-priority interrupt serviced first
16-Input Priority Encoder: Two 74148s; inputs 8-15 on higher-priority, 0-7 on lower; cascaded via EO→EI; outputs combined with NAND gates for 4-bit result
Keyboard Encoder: 8 keys → inputs 0-7; A2-A0 = key code; GS = key-pressed flag; no multiple-key ambiguity
Active-Low Detection: 8 fault lines → inputs; GS = any fault active; A2-A0 = highest-priority fault code

Alternative Models:What chips are recommended as replacements for SN74LS148N

Modelo	Fabricante	Diferencia clave	Paquete	Supply
74LS148N	TI/Nexperia	Original TTL version with 5V-only supply, typical propagation delay 10-15ns	DIP-16	5V TTL
74LS148D	TI/Nexperia	Surface-mount SOIC version of LS with identical logic function	SOIC-16	5V TTL
74HC148D	TI/Nexperia	CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity	SOIC-16	2-6V CMOS
74HC148N	TI/Nexperia	Through-hole DIP version of HC family for prototyping and repair	DIP-16	2-6V CMOS
74HCT148D	TI/Nexperia	CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V	SOIC-16	4.5-5.5V TTL-in
74HCT148N	TI/Nexperia	Through-hole DIP version of HCT family for prototyping and repair	DIP-16	4.5-5.5V TTL-in

The 74148 is a 8-Line to 3-Line Priority Encoder. Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.