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SN74LS138N

3-to-8 decoder/demux, active-low outputs, 3 enable inputs, 22ns, PDIP-16

15600

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Pieza del fabricante：

SN74LS138N

Paquete：

PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch)

Marca：

Categorías de productos：

Circuitos integrados IC, Circuitos integrados de interfaz

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Descripción

Productos

The SN74LS138N is a 3-line to 8-line decoder/demultiplexer from Texas Instruments with active-low outputs, three enable inputs, and 22ns typical propagation delay in a 16-pin PDIP through-hole package.

Especificaciones

Función	3-to-8 line decoder/demultiplexer
Select Inputs	3 (A, B, C)
Outputs	8 (active low)
Enable Inputs	3 (G1 active high, G2A and G2B active low)
Retardo de propagación	22ns typical, 41ns max
Tensión de alimentación	4.75V to 5.25V (5V nominal)
Supply Current	6.1mA typical (ICC)
Output Drive	8mA sink, 0.4mA source
Logic Family	74LS (Low-power Schottky)
Temperatura de funcionamiento	0°C to +70°C
Paquete	PDIP-16 (19.3 x 6.35mm, through-hole)

Características

Three enable inputs for flexible cascading and demultiplexing
Active-low outputs simplify chip-select generation
Demultiplexing capability with data input on enable
Full decoding of input combinations (no don’t-care states)
Standard 74LS Schottky TTL technology
Multiple devices easily cascaded for larger decoding
Industry-standard pinout and function
Low 6.1mA typical supply current

Aplicaciones

Memory address decoding
I/O port selection in microprocessor systems
Data demultiplexing and routing
Chip-select generation for multiple peripherals
Display digit selection

Introducción del producto:SN74LS138N Presentación del producto

The SN74LS138N is a 3-line to 8-line decoder/demultiplexer from Texas Instruments in the 74LS Low-power Schottky TTL family. It decodes a 3-bit binary input (A, B, C) into one of eight mutually exclusive active-low outputs (Y0-Y7). Three enable inputs (G1 active high, G2A and G2B active low) provide flexible cascading for larger decoding functions and allow the device to be used as a 1-to-8 demultiplexer by applying data to an enable input. The 22ns typical propagation delay supports microprocessor clock rates up to tens of MHz. The PDIP-16 through-hole package is ideal for prototyping and educational applications.

Principio de funcionamiento:SN74LS138N Principio de funcionamiento

The SN74LS138N uses AND-OR-INVERT logic to implement the 3-to-8 decoding function. The three select inputs (A, B, C) are decoded by eight 3-input AND gates, each producing one of the eight minterms. Each AND gate also includes the enable conditions: G1 must be high, and both G2A and G2B must be low for any output to be active. When enabled, exactly one of the eight outputs is driven low (active) corresponding to the binary value on the select inputs, while all other outputs remain high. When disabled (any enable condition not met), all outputs are forced high regardless of the select inputs. For demultiplexer operation, the data signal is applied to one of the enable inputs (typically G1), while the other enables are held in the active state. The data signal is then routed to the output selected by the A, B, C inputs. The 74LS Schottky TTL technology uses Schottky-clamped transistors to prevent saturation, reducing propagation delay to 22ns typical while maintaining reasonable power consumption at 6.1mA ICC.

Descripción de la clavija:SN74LS138N Definición y funciones de las clavijas

Pin	Nombre	Tipo	Descripción
1-3	A, B, C	Entrada	Select inputs (A=LSB, C=MSB)
4-6	G2A, G2B, G1	Entrada	Enable inputs (G2A, G2B active low; G1 active high)
7	Y7	Salida	Decoded output 7 (active low)
8	GND	Potencia	Suelo
9-11	Y6-Y4	Salida	Decoded outputs 6, 5, 4 (active low)
12-14	Y3-Y1	Salida	Decoded outputs 3, 2, 1 (active low)
15	Y0	Salida	Decoded output 0 (active low)
16	VCC	Potencia	Supply voltage (5V)

Application Scenarios:In which products and applications isSN74LS138N usado

Memory Decoding: 3 select inputs decode 8 memory banks; active-low outputs directly drive chip-enable pins on SRAM and EPROM
I/O Port Selection: Decodes microprocessor address lines to select one of eight I/O ports or peripheral chips
Data Demultiplexing: Data applied to G1 is routed to the output selected by A, B, C for serial-to-parallel distribution
Cascaded Decoding: Two 74LS138 devices cascade to form a 4-to-16 decoder using enable inputs for the MSB
Display Multiplexing: Active-low outputs select one of eight digit drivers in multiplexed LED displays

Alternative Models:What chips are recommended as replacements for SN74LS138N

Modelo	Fabricante	Diferencia clave	Paquete	Supply
74LS138N	TI/Nexperia	Original TTL version with 5V-only supply, typical propagation delay 10-15ns	DIP-16	5V TTL
74LS138D	TI/Nexperia	Surface-mount SOIC version of LS with identical logic function	SOIC-16	5V TTL
74HC138D	TI/Nexperia	CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity	SOIC-16	2-6V CMOS
74HC138N	TI/Nexperia	Through-hole DIP version of HC family for prototyping and repair	DIP-16	2-6V CMOS
74HCT138D	TI/Nexperia	CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V	SOIC-16	4.5-5.5V TTL-in
74HCT138N	TI/Nexperia	Through-hole DIP version of HCT family for prototyping and repair	DIP-16	4.5-5.5V TTL-in
74AC138D	TI/Nexperia	Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC)	SOIC-16	2-6V CMOS
74AC138N	TI/Nexperia	Through-hole DIP version of AC family for prototyping and repair	DIP-16	2-6V CMOS
74LVC138D	TI/Nexperia	Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs	SOIC-16	1.65-3.6V CMOS
74LVC138N	TI/Nexperia	Through-hole DIP version of LVC family for prototyping and repair	DIP-16	1.65-3.6V CMOS

The 74138 is a 3-Line to 8-Line Decoder/Demultiplexer. Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.