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SN74LS112N

Dual J-K flip-flop, negative-edge, preset/clear, PDIP-16

3500

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Pieza del fabricante：

SN74LS112N

Paquete：

PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

Marca：

Categorías de productos：

Circuitos integrados IC, Circuitos integrados de interfaz

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Descripción

Productos

The SN74LS112N from Texas Instruments is a dual negative-edge-triggered J-K flip-flop with preset and clear inputs, capable of toggle, latch, and shift register functions in a 16-pin PDIP package.

Especificaciones

Number of Flip-Flops	2 (dual, independent)
Logic Family	LS (Low-power Schottky)
Trigger Type	Negative-edge (falling edge of CLK)
Tensión de alimentación	4.75V to 5.25V
Max Clock Frequency	30MHz typical
Preset (PRE)	Active LOW (asynchronous, sets Q=1)
Clear (CLR)	Active LOW (asynchronous, sets Q=0)
Temperatura de funcionamiento	0°C to +70°C
Paquete	PDIP-16 (19.3 x 6.35mm)

Características

Dual J-K flip-flops, negative-edge triggered
Asynchronous preset and clear
J-K inputs: toggle mode (J=K=1), hold (J=K=0), set (J=1,K=0), reset (J=0,K=1)
30MHz maximum clock frequency

Aplicaciones

Frequency divider (toggle mode)
Shift register building block
Counter building block
Event latch

Introducción del producto:SN74LS112N Presentación del producto

The SN74LS112N from Texas Instruments contains two independent negative-edge-triggered J-K flip-flops with asynchronous preset (PRE, active LOW) and clear (CLR, active LOW) inputs. The J-K flip-flop is the most versatile flip-flop type: it can toggle (J=K=1), hold its state (J=K=0), set (J=1, K=0), or reset (J=0, K=1). In toggle mode, the output divides the clock frequency by 2, making it ideal for frequency dividers and binary counter chains. The negative-edge trigger means the output changes on the falling edge of the clock, which is important for cascaded counters where ripple delays must be accommodated. The asynchronous PRE and CLR inputs override the clocked operation: PRE forces Q=1 regardless of J, K, or CLK; CLR forces Q=0. Both PRE and CLR should be HIGH for normal clocked operation. The N suffix denotes the PDIP-16 through-hole package.

Principio de funcionamiento:SN74LS112N Principio de funcionamiento

Each J-K flip-flop in the SN74LS112N operates on the falling edge of the clock. The J and K inputs are sampled just before the falling edge, and the output transitions according to: J=0,K=0: Q holds (no change); J=0,K=1: Q goes to 0 (reset); J=1,K=0: Q goes to 1 (set); J=1,K=1: Q toggles (inverts). The setup time requirement means J and K must be stable for at least 20ns before the falling clock edge. The hold time requirement (typically 0ns for LS) means J and K must remain stable for 0ns after the falling edge. In toggle mode (J=K=1), each falling clock edge inverts Q, so the output completes one full cycle for every two clock cycles — a divide-by-2 function. Cascading two toggle flip-flops creates a divide-by-4; three creates divide-by-8, etc. The asynchronous PRE (preset) input forces Q=1 immediately when brought LOW, regardless of the clock. Similarly, CLR (clear) forces Q=0. If both PRE and CLR are LOW simultaneously, both Q and NOT-Q go HIGH (invalid state); the final state after both are released is indeterminate.

Descripción de la clavija:SN74LS112N Definición y funciones de las clavijas

Pin	Nombre	Tipo	Descripción
1	1CLK	Entrada	Flip-flop 1 clock (falling edge triggered)
2	1K	Entrada	Flip-flop 1 K input
3	1J	Entrada	Flip-flop 1 J input
4	1PRE	Entrada	Flip-flop 1 preset (active LOW, sets Q=1)
5	1Q	Salida	Flip-flop 1 Q output
6	1NOT-Q	Salida	Flip-flop 1 NOT-Q output
7	1CLR	Entrada	Flip-flop 1 clear (active LOW, sets Q=0)
8	GND	Potencia	Suelo
9	2CLR	Entrada	Flip-flop 2 clear (active LOW)
10	2NOT-Q	Salida	Flip-flop 2 NOT-Q output
11	2Q	Salida	Flip-flop 2 Q output
12	2PRE	Entrada	Flip-flop 2 preset (active LOW)
13	2J	Entrada	Flip-flop 2 J input
14	2K	Entrada	Flip-flop 2 K input
15	2CLK	Entrada	Flip-flop 2 clock (falling edge)
16	VCC	Potencia	Supply (5V)

Application Scenarios:In which products and applications isSN74LS112N usado

Divide-by-2: J=K=1 (tie to VCC); CLK input; Q output = CLK/2; cascaded for divide-by-4, -8, -16…
T-Flip-Flop: Same as toggle mode; used for frequency division
Data Latch: J=D (data), K=NOT-D; CLK falling edge latches D into Q; D-type flip-flop behavior
Shift Register: 1Q connects to 2J; 1NOT-Q to 2K; serial data into 1J/1K; two-stage shift register

Alternative Models:What chips are recommended as replacements for SN74LS112N

Modelo	Fabricante	Diferencia clave	Paquete	Supply
74LS112N	TI/Nexperia	Original TTL version with 5V-only supply, typical propagation delay 10-15ns	DIP-16	5V TTL
74LS112D	TI/Nexperia	Surface-mount SOIC version of LS with identical logic function	SOIC-16	5V TTL
74HC112D	TI/Nexperia	CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity	SOIC-16	2-6V CMOS
74HC112N	TI/Nexperia	Through-hole DIP version of HC family for prototyping and repair	DIP-16	2-6V CMOS
74HCT112D	TI/Nexperia	CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V	SOIC-16	4.5-5.5V TTL-in
74HCT112N	TI/Nexperia	Through-hole DIP version of HCT family for prototyping and repair	DIP-16	4.5-5.5V TTL-in

The 74112 is a Dual Negative-Edge-Triggered J-K Flip-Flop. Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.