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SN74LS10N

Triple 3-input NAND gate, LS TTL, 12ns, PDIP-14

5000

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Pieza del fabricante：

SN74LS10N

Paquete：

PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

Marca：

Categorías de productos：

Circuitos integrados IC, Circuitos integrados de interfaz

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Descripción

Productos

The SN74LS10N from Texas Instruments is a triple 3-input positive NAND gate with LS TTL technology, 12ns propagation delay, and industry-standard 7410 pinout in a 14-pin PDIP package.

Especificaciones

Number of Gates	3 (triple 3-input NAND)
Logic Family	LS (Low-power Schottky)
Tensión de alimentación	4.75V to 5.25V (5V nominal)
Retardo de propagación	12ns typical @ 5V
Output Drive (IOL/IOH)	8mA / -0.4mA
Temperatura de funcionamiento	0°C to +70°C
Paquete	PDIP-14 (19.3 x 6.35mm)

Características

Three independent 3-input NAND gates
LS TTL technology
12ns typical propagation delay
Industry-standard 7410 pinout

Aplicaciones

3-input majority logic
Active-low signal combination
Address decoding
General-purpose combinational logic

Introducción del producto:SN74LS10N Presentación del producto

The SN74LS10N from Texas Instruments contains three independent 3-input NAND gates in a 14-pin PDIP package. Each gate performs Y = NOT(A AND B AND C); the output is LOW only when ALL three inputs are HIGH. The 3-input NAND is essential for majority logic and multi-condition gating where an action requires multiple conditions to be met simultaneously. Unlike the 2-input 7400, the 7410 tests for conjunction of three signals, useful in address decoding where three address lines must all be HIGH to select a particular memory range. The N suffix denotes the PDIP-14 through-hole package.

Principio de funcionamiento:SN74LS10N Principio de funcionamiento

Each 3-input NAND gate in the SN74LS10N performs Y = A NAND B NAND C = NOT(A AND B AND C). The truth table has 8 entries: the output is LOW only for the single case A=B=C=HIGH (111→0); for all other 7 input combinations, the output is HIGH. This makes the 3-input NAND a natural majority detector with inverted output: it detects when all three inputs agree (are HIGH). For an active-LOW AND (output goes LOW when all inputs are HIGH), the 3-input NAND is used directly. For a 3-input AND (output goes HIGH when all inputs are HIGH), add an inverter after the NAND, or use one gate of a 7404. For majority logic (output HIGH when 2 or more of 3 inputs are HIGH), a more complex circuit using multiple gates is needed.

Descripción de la clavija:SN74LS10N Definición y funciones de las clavijas

Pin	Nombre	Tipo	Descripción
1	1A	Entrada	Gate 1 input A
2	1B	Entrada	Gate 1 input B
3	2A	Entrada	Gate 2 input A
4	2B	Entrada	Gate 2 input B
5	2C	Entrada	Gate 2 input C
6	2Y	Salida	Gate 2 output (NAND)
7	GND	Potencia	Suelo
8	3Y	Salida	Gate 3 output (NAND)
9	3A	Entrada	Gate 3 input A
10	3B	Entrada	Gate 3 input B
11	3C	Entrada	Gate 3 input C
12	1Y	Salida	Gate 1 output (NAND)
13	1C	Entrada	Gate 1 input C
14	VCC	Potencia	Supply (4.75V to 5.25V)

Application Scenarios:In which products and applications isSN74LS10N usado

3-Condition Gate: Output LOW only when all 3 conditions (inputs) are HIGH; e.g., chip select = /CS when A15=A14=A13=1
3-Input AND: NAND gate + inverter; Y = A AND B AND C; all three must be HIGH for HIGH output
Address Decode: Three high-order address bits → 3-input NAND; output LOW when specific address range selected
Strobe Gate: Data signal on one input, two enable signals on others; output active only when both enables HIGH

Alternative Models:What chips are recommended as replacements for SN74LS10N

Modelo	Fabricante	Diferencia clave	Paquete	Supply
74LS10N	TI/Nexperia	Original TTL version with 5V-only supply, typical propagation delay 10-15ns	DIP-14	5V TTL
74LS10D	TI/Nexperia	Surface-mount SOIC version of LS with identical logic function	SOIC-14	5V TTL
74HC10D	TI/Nexperia	CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity	SOIC-14	2-6V CMOS
74HC10N	TI/Nexperia	Through-hole DIP version of HC family for prototyping and repair	DIP-14	2-6V CMOS
74HCT10D	TI/Nexperia	CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V	SOIC-14	4.5-5.5V TTL-in
74HCT10N	TI/Nexperia	Through-hole DIP version of HCT family for prototyping and repair	DIP-14	4.5-5.5V TTL-in
74AC10D	TI/Nexperia	Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC)	SOIC-14	2-6V CMOS
74AC10N	TI/Nexperia	Through-hole DIP version of AC family for prototyping and repair	DIP-14	2-6V CMOS

The 7410 is a Triple 3-Input NAND Gate. Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.