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SN74LS02N

Quad 2-input NOR gate, LS TTL, 15ns, PDIP-14

5500

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Pieza del fabricante：

SN74LS02N

Paquete：

PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)

Marca：

Categorías de productos：

Circuitos integrados IC, Circuitos integrados de interfaz

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Descripción

Productos

The SN74LS02N from Texas Instruments is a quad 2-input NOR gate with LS TTL technology, 15ns propagation delay, and industry-standard 7402 pinout in a 14-pin PDIP package.

Especificaciones

Number of Gates	4 (quad 2-input NOR)
Logic Family	LS (Low-power Schottky)
Tensión de alimentación	4.75V to 5.25V (5V nominal)
Retardo de propagación	15ns typical @ 5V
Output Drive (IOL/IOH)	8mA / -0.4mA
Temperatura de funcionamiento	0°C to +70°C
Paquete	PDIP-14 (19.3 x 6.35mm)

Características

Four independent 2-input NOR gates
LS TTL technology
15ns typical propagation delay
Industry-standard 7402 pinout

Aplicaciones

Logic NOR function implementation
Active-low signal OR (negative logic AND)
SR latch construction
Address decoding with active-low outputs
General-purpose logic gating

Introducción del producto:SN74LS02N Presentación del producto

The SN74LS02N from Texas Instruments contains four independent 2-input NOR gates in a 14-pin PDIP through-hole package. Each gate performs the Boolean function Y = NOT(A OR B); the output is HIGH only when both inputs are LOW. By DeMorgan’s theorem, a NOR gate also functions as an AND gate in negative logic: Y = A (negative-AND) B, where the output is LOW when either input is HIGH. This makes NOR gates useful for combining active-low signals such as chip selects and interrupt lines. The NOR gate is also a universal gate: any Boolean function can be implemented using only NOR gates (or only NAND gates). Two NOR gates cross-coupled form an SR latch, the simplest sequential logic element. The N suffix denotes the PDIP-14 through-hole package.

Principio de funcionamiento:SN74LS02N Principio de funcionamiento

Each NOR gate in the SN74LS02N performs the Boolean function Y = A NOR B = NOT(A OR B). The output is HIGH only when both inputs are LOW. The truth table is: 00→1, 01→0, 10→0, 11→0. By DeMorgan’s theorem, A NOR B = NOT(A) AND NOT(B), meaning the NOR gate is equivalent to an AND gate with inverted inputs. This dual interpretation is useful in active-low logic systems common in TTL design. Two NOR gates cross-coupled form a basic SR latch: if S (set) goes HIGH, Q goes HIGH; if R (reset) goes HIGH, Q goes LOW. When both S and R are LOW, the latch holds its previous state. The NOR gate is a universal gate: an inverter is a NOR gate with both inputs tied together; an OR gate is a NOR gate followed by an inverter; an AND gate is a NOR gate with inverted inputs (which are themselves NOR-based inverters).

Descripción de la clavija:SN74LS02N Definición y funciones de las clavijas

Pin	Nombre	Tipo	Descripción
1	1Y	Salida	Gate 1 output (NOR)
2	1A	Entrada	Gate 1 input A
3	1B	Entrada	Gate 1 input B
4	2Y	Salida	Gate 2 output (NOR)
5	2A	Entrada	Gate 2 input A
6	2B	Entrada	Gate 2 input B
7	GND	Potencia	Suelo
8	3A	Entrada	Gate 3 input A
9	3B	Entrada	Gate 3 input B
10	3Y	Salida	Gate 3 output (NOR)
11	4A	Entrada	Gate 4 input A
12	4B	Entrada	Gate 4 input B
13	4Y	Salida	Gate 4 output (NOR)
14	VCC	Potencia	Supply (4.75V to 5.25V)

Application Scenarios:In which products and applications isSN74LS02N usado

SR Latch: Two NOR gates cross-coupled; S=HIGH sets Q=HIGH; R=HIGH resets Q=LOW; basic memory element
Active-Low OR: Two active-low enables NORed; output goes HIGH only when BOTH enables are inactive (deasserted)
Power-On Reset: RC on one input; other input HIGH; output HIGH during power-up, LOW after cap charges
Decoder: NOR of decoded address bits; output HIGH only when all address bits are LOW (specific address)
Inverter: Tie both inputs together; NOR(A, A) = NOT(A); saves using a 7404 inverter

Alternative Models:What chips are recommended as replacements for SN74LS02N

Modelo	Fabricante	Diferencia clave	Paquete	Supply
74LS02N	TI/Nexperia	Original TTL version with 5V-only supply, typical propagation delay 10-15ns	DIP-14	5V TTL
74LS02D	TI/Nexperia	Surface-mount SOIC version of LS with identical logic function	SOIC-14	5V TTL
74HC02D	TI/Nexperia	CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity	SOIC-14	2-6V CMOS
74HC02N	TI/Nexperia	Through-hole DIP version of HC family for prototyping and repair	DIP-14	2-6V CMOS
74HCT02D	TI/Nexperia	CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V	SOIC-14	4.5-5.5V TTL-in
74HCT02N	TI/Nexperia	Through-hole DIP version of HCT family for prototyping and repair	DIP-14	4.5-5.5V TTL-in
74AC02D	TI/Nexperia	Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC)	SOIC-14	2-6V CMOS
74AC02N	TI/Nexperia	Through-hole DIP version of AC family for prototyping and repair	DIP-14	2-6V CMOS
74LVC02D	TI/Nexperia	Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs	SOIC-14	1.65-3.6V CMOS
74LVC02N	TI/Nexperia	Through-hole DIP version of LVC family for prototyping and repair	DIP-14	1.65-3.6V CMOS

The 7402 is a Quad 2-Input NOR Gate. Family variants span from the original LS TTL (5V only) to modern LVC/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.