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SI4909DY-T1-GE3

Dual P-ch MOSFET, 40V/8A, 27mohm, logic-level, SOIC-8

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Pieza del fabricante：

SI4909DY-T1-GE3

Paquete：

8-Pin SOIC (5.0 x 4.0 x 1.5 mm)

Marca：
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Descripción

Productos

The SI4909DY-T1-GE3 is a Vishay Siliconix dual P-channel 40V TrenchFET power MOSFET with 8A continuous drain current and 27mohm max RDS(on) at VGS=-10V. Logic-level gate threshold. Packaged in SOIC-8, -55C to +150C junction temperature.

Especificaciones

Configuración Dual P-channel
VDS -40 V
ID -8 A per channel
RDS(on) 27 mohm max @ -10V
Qg 63 nC max
PD 3.2 W

Características

  • Dual P-channel in SOIC-8
  • 40V drain-source voltage
  • 8A continuous drain current
  • 27mohm max RDS(on)
  • Logic-level gate drive
  • 100% Rg and UIS tested
  • Halogen-free

Aplicaciones

  • Load switches and battery disconnect
  • Notebook and desktop PC power
  • DC-DC converter high-side switches
  • Battery management load switching

The SI4909DY-T1-GE3 is a Vishay Siliconix dual P-channel TrenchFET power MOSFET in an SOIC-8 package, providing two independent P-channel MOSFETs with 40V drain-source rating and 8A continuous drain current per channel. The 27mohm maximum on-resistance at VGS=-10V ensures low conduction losses in load switch and DC-DC converter applications. The logic-level gate threshold enables direct drive from 3.3V or 5V microcontroller GPIOs. The TrenchFET trench-gate architecture achieves low RDS(on) in a compact footprint compared to planar MOSFETs. The two P-channel MOSFETs share a common source (pins 1,2,3) with independent gates and drains, making the device ideal for complementary pair or high-side switch applications. The -T1-GE3 suffix indicates tape-and-reel, halogen-free, and RoHS-compliant packaging. Each device is 100% Rg and UIS tested for reliability. Rated for -55C to +150C junction temperature.

The SI4909DY contains two independent P-channel enhancement-mode TrenchFET MOSFETs. Each MOSFET conducts when the gate-source voltage is more negative than the threshold voltage (typically -1.2V). When VGS = -10V (full enhancement), the channel resistance is 27mohm maximum, allowing 8A current with minimal voltage drop and power dissipation. In the off state (VGS = 0V or positive), the drain-source channel blocks voltage up to 40V with only nanoampere leakage current. The TrenchFET trench-gate structure uses vertical trenches etched into the silicon, with the gate electrode inside the trench. This geometry increases channel width per unit area, reducing RDS(on) for a given die size compared to planar structures. The body diode (inherent PN junction between body and drain) provides a reverse conduction path, useful in free-wheeling applications but may require consideration in reverse-polarity protection circuits.

Pin Mnemonic Descripción
1 S1 Source 1 (common with S2)
2 G1 Puerta 1
3 S2 Source 2
4 G2 Puerta 2
5 D2 Drenaje 2
6 D2 Drain 2 (parallel)
7 D1 Drain 1 (parallel)
8 D1 Drenaje 1
  • Battery disconnect and load switch with dual P-channel high-side switching
  • Notebook PC power management with logic-level gate drive from 3.3V
  • DC-DC buck converter high-side P-channel switch with 27mohm RDS(on)
  • Battery management system load switching with 40V rating
Modelo Fabricante Diferencia clave
SI4920DY-T1-GE3 Vishay Dual N+P complement
SI4947DY Vishay Dual P, lower RDS(on)
IRF7319 Infineon Dual P, 30V, similar
FDS8933 onsemi Dual P, 30V, similar
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