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DP83848KSQ

10/100 Ethernet PHY, MII/RMII, Auto-MDIX, LQFP-48

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Pieza del fabricante：

DP83848KSQ

Paquete：

LQFP-48 (7.0 x 7.0 x 1.4 mm)

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Descripción

Productos

The DP83848KSQ from Texas Instruments is a 10/100 Ethernet PHY transceiver with MII/RMII interface, IEEE 802.3u compliance, and LQFP-48 package.

Especificaciones

Tipo 10/100 Ethernet PHY Transceiver
Speed 10 Mbps and 100 Mbps
MAC Interface MII / RMII
Standards IEEE 802.3u, IEEE 802.3x
Auto-Negotiation Yes
Auto-MDIX Yes (auto crossover)
Tensión de alimentación 3.3V (I/O); 1.8V (core, internal regulator)
Current Consumption 130 mA (typical, 100Mbps active)
Paquete LQFP-48 (7 x 7 mm)
Temperatura de funcionamiento -40C to +85C (I grade, K suffix)

Características

  • 10/100Mbps Ethernet PHY with auto-negotiation
  • MII and RMII MAC interface support
  • Auto-MDIX for automatic TX/RX crossover
  • IEEE 802.3u compliant
  • Integrated 1.8V core voltage regulator
  • 25MHz crystal or oscillator input

Aplicaciones

  • Embedded Ethernet connectivity
  • Industrial networking
  • IoT gateways
  • Network-enabled microcontroller systems

The DP83848KSQ from Texas Instruments (formerly National Semiconductor) is a robust 10/100 Mbps Ethernet physical layer transceiver designed for embedded networking applications. The device provides a complete PHY solution with integrated 100Base-TX and 10Base-T transceivers, supporting both MII (Media Independent Interface) and RMII (Reduced MII) connections to the MAC layer. Auto-negotiation automatically selects the best available speed and duplex mode. Auto-MDIX eliminates the need for crossover cables by automatically detecting and correcting TX/RX pair polarity. The integrated 1.8V core voltage regulator simplifies the power supply design to a single 3.3V rail. The device is compliant with IEEE 802.3u and IEEE 802.3x standards. The LQFP-48 package provides adequate pin spacing for manufacturing ease while maintaining a compact footprint.

The DP83848KSQ implements the physical layer of the Ethernet protocol stack. For 100Base-TX operation, the transmitter encodes 4-bit nibbles from the MII into 5-bit symbols using 4B/5B encoding, scrambles the data, and converts it to MLT-3 (Multi-Level Transmit) three-level signaling for transmission over the twisted pair. The receiver performs the reverse: equalization, MLT-3 decoding, descrambling, and 5B/4B decoding to recover the MII nibbles. For 10Base-T, Manchester encoding is used. The auto-negotiation protocol (IEEE 802.3u) exchanges capability information with the link partner using Fast Link Pulses (FLP) to determine the highest common speed and duplex mode. Auto-MDIX detects whether the cable is straight-through or crossover by measuring the received signal polarity on the TX pair and swapping the TX/RX pairs if needed. The internal PLL generates all required clock frequencies from the 25 MHz input reference.

Grupo Pin Nombre Tipo Función
MAC TXD[0:3]/TXD[0:1] Entrada MII/RMII transmit data
MAC RXD[0:3]/RXD[0:1] Salida MII/RMII receive data
MAC TX_CLK/TX_EN E/S MII clock/Transmit enable
MAC RX_CLK/RX_DV Salida MII clock/Receive data valid
MAC MDC/MDIO E/S Management interface (SMI)
Line TXP/TXN Salida Differential transmit pair
Line RXP/RXN Entrada Differential receive pair
Reloj X1/X2 E/S 25 MHz crystal/oscillator
Potencia VDD/AVDD Potencia 3.3V supply
  • STM32F4 Ethernet connectivity with RMII interface and Auto-MDIX
  • Industrial Modbus TCP gateway with 10/100Mbps PHY and auto-negotiation
  • IoT smart home hub with Ethernet backhaul and 130mA active current
  • Embedded web server with MII interface to custom FPGA MAC
Fabricante Número de pieza Paquete Notas
TI DP83848CVV LQFP-48 Commercial temp version
Microchip KSZ8041NLIA QFN-32 10/100 PHY, smaller package
Realtek RTL8201F-VB-CG QFN-32 10/100 PHY, lower cost
Microchip KSZ9031RNXIA QFN-48 Gigabit PHY upgrade
TI DP83867IR QFN-48 Gigabit PHY, RGMII
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