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CD4070BM96

Quad 2-input XOR gate, 3-18V CMOS, 65ns at 10V, SOIC-14

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Pieza del fabricante：

CD4070BM96

Paquete：

SOIC-14 (8.75 x 3.9 x 1.5mm)

Marca：
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Descripción

Productos

The CD4070BM96 from Texas Instruments is a quad Exclusive-OR (XOR) gate in the 4000B CMOS family. Operating from 3V to 18V, it provides four independent 2-input XOR gates with medium-speed operation (65ns propagation at 10V) in a SOIC-14 package.

Especificaciones

Logic Function Quad 2-input Exclusive-OR (XOR)
Tensión de alimentación 3V to 18V
Retardo de propagación 65ns typ at VDD=10V, CL=50pF
Input Current (Max) 1uA at 18V over full temperature
Noise Margin 1V at 5V, 2V at 10V, 2.5V at 15V
Temperatura de funcionamiento -55 to 125 C
Paquete SOIC-14

Características

  • Wide 3V to 18V supply voltage range
  • Standardized symmetrical output characteristics
  • 100% tested for quiescent current at 20V
  • Meets JEDEC Standard No. 13B for B-series CMOS

Aplicaciones

  • Logic comparators and equality detectors
  • Binary adders and subtractors
  • Parity generators and checkers
  • Control and sequencing logic
  • Edge detection circuits

The CD4070BM96 from Texas Instruments contains four independent Exclusive-OR (XOR) gates in a single SOIC-14 package. As a member of the 4000B CMOS logic family, it operates over a wide 3V to 18V supply range with very low input current (1uA max at 18V). The XOR function outputs HIGH when the two inputs are different, making it essential for comparison, parity, and arithmetic logic circuits. The device features medium-speed operation with 65ns typical propagation delay at 10V supply and 50pF load capacitance.

The CD4070BM96 implements four independent Exclusive-OR gates using CMOS technology. **XOR Logic**: Each gate outputs a logic HIGH when its two inputs differ (A=0,B=1 or A=1,B=0), and outputs LOW when inputs are the same (A=0,B=0 or A=1,B=1). The Boolean expression is Y = A XOR B = A*B’ + A’*B. **CMOS Implementation**: Each XOR gate is constructed from complementary N-channel and P-channel MOSFET pairs. The CMOS structure provides rail-to-rail output swing, very low static power consumption, and symmetrical output drive capability. **Wide Supply Range**: The 3V to 18V operating range makes the device compatible with both 5V TTL-level systems and higher-voltage industrial logic. The noise margin increases proportionally with supply voltage. **Propagation Delay**: The 65ns typical delay at 10V is adequate for moderate-speed logic applications. Delay increases at lower supply voltages and higher load capacitances.

Pin Nombre Descripción
1 A1 Gate 1 Input A
2 B1 Gate 1 Input B
3 Y1 Gate 1 Output (A1 XOR B1)
4 A2 Gate 2 Input A
5 B2 Gate 2 Input B
6 Y2 Gate 2 Output
7 VSS Suelo
8 Y3 Gate 3 Output
9 A3 Gate 3 Input A
10 B3 Gate 3 Input B
11 Y4 Gate 4 Output
12 A4 Gate 4 Input A
13 B4 Gate 4 Input B
14 VDD Power supply (3V to 18V)
  • Parity Checking: Generating and verifying parity bits for error detection in data communication
  • Binary Arithmetic: Half-adder and full-adder sum bit generation in binary addition circuits
  • Comparator: Detecting inequality between two binary words for address decoding
  • Edge Detection: Generating pulses on signal transitions for event detection and clock extraction
Modelo Fabricante Diferencia clave
CD4070BPWR TI TSSOP-14, smaller package
74HC86D Nexperia Quad XOR, 2-6V HC family, faster
74LVC2G86DP Nexperia Dual XOR, 1.65-5.5V, TSSOP-8
MC14070BDR2G onsemi Same function, SOIC-14
HEF4070BT Nexperia Same function, SOIC-14
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