Inicio > Circuitos integrados IC > CD4011UBM

CD4011UBM

Quad 2-input NAND, CMOS 4000-series, 3-18V, SOIC-14

10800

Inventario efectivo

Ir a la consulta

Image for reference only

Pieza del fabricante：

CD4011UBM

Paquete：

SOIC-14 (8.75 x 3.91 x 1.50 mm)

Marca：

Categorías de productos：

Circuitos integrados IC

Otras recomendaciones que pueden interesarle.

SII9396SCNUC-BAR

IS43TR16256BL-125KBLI

Descripción

Productos

The CD4011UBM from Texas Instruments is a CMOS quad 2-input NAND gate operating from 3V to 18V supply with low power consumption and balanced propagation delay in a 14-pin SOIC package.

Especificaciones

Logic Function	Quad 2-input NAND
Tensión de alimentación	3 V to 18 V
Retardo de propagación	65 ns typical @ 10V
Corriente de salida	+/-0.88 mA @ 5V, +/-2.25 mA @ 10V
Input Current	+/-0.1 uA @ 18V, 25°C
Corriente de reposo	0.02 uA typical @ 5V
Noise Immunity	45% of VDD typical
Temperatura de funcionamiento	-55°C to +125°C
Paquete	SOIC-14

Características

Standard 4000-series CMOS quad NAND gate with 3-18V supply range
Very low quiescent current (20nA typical) and high noise immunity

Aplicaciones

General-purpose logic in industrial and battery-powered systems

Introducción del producto:CD4011UBM Presentación del producto

The CD4011UBM from Texas Instruments is a standard 4000-series CMOS quad 2-input NAND gate. The device contains four independent 2-input NAND gates in a single 14-pin SOIC package. The wide 3V to 18V supply voltage range makes it suitable for interfacing between different logic voltage domains and for use in battery-powered or industrial systems with non-standard supply voltages. The very low quiescent current (20nA typical at 5V) is ideal for always-on circuits. The high noise immunity (45% of VDD) provides reliable operation in electrically noisy environments. The UB designation indicates the unbuffered output version, which provides a single-stage output with slightly faster propagation delay but lower output drive than the buffered (B) version. The M suffix denotes the SOIC-14 surface-mount package.

Principio de funcionamiento:CD4011UBM Principio de funcionamiento

The CD4011UBM implements four independent 2-input NAND gates using CMOS technology. (1) NAND Function: Each gate produces a LOW output only when both inputs are HIGH. The boolean expression is Y = NOT(A AND B). (2) CMOS Structure: Each NAND gate uses a pull-up network of two PMOS transistors in parallel and a pull-down network of two NMOS transistors in series. When both inputs are HIGH, both NMOS transistors conduct and both PMOS transistors are off, pulling the output LOW. For any other input combination, at least one PMOS conducts and the series NMOS path is broken, pulling the output HIGH. (3) Unbuffered Output: The UB version uses a single CMOS inverter stage at the output rather than the cascaded buffer stages of the B version. This provides lower propagation delay at the cost of reduced output drive current and asymmetric rise/fall times when driving capacitive loads. (4) Wide Supply: The CMOS structure allows operation from 3V to 18V, with all switching thresholds and output levels proportional to the supply voltage.

Descripción de la clavija:CD4011UBM Definición y funciones de las clavijas

Pin	Nombre	Función
1	A1	Gate 1 input A
2	B1	Gate 1 input B
3	Y1	Gate 1 output
4	Y2	Gate 2 output
5	A2	Gate 2 input A
6	B2	Gate 2 input B
7	VSS	Suelo
8	A3	Gate 3 input A
9	B3	Gate 3 input B
10	Y3	Gate 3 output
11	Y4	Gate 4 output
12	A4	Gate 4 input A
13	B4	Gate 4 input B
14	VDD	Positive supply (3-18V)