CSD87330Q3D

The CSD87330Q3D is a NexFET power block from Texas Instruments that integrates a half-bridge MOSFET pair in a compact 3.3×3.3-mm LSON package. It is the smaller sibling of the CSD87350Q5D (5×6 mm, 40 A), targeting 15-20 A synchronous buck applications where board space is at a premium.

The power block approach integrates both the control FET and sync FET in one package with a copper-clip internal interconnect, reducing parasitic inductance between the two MOSFETs to sub-100 pH. This eliminates the switch-node ringing and overshoot typical of discrete MOSFET solutions, enabling higher switching frequencies and smaller output filter components.

The control FET (Q1) is optimized for low switching losses with gate charge of 4.8 nC typical at 4.5 V, while the sync FET (Q2) is optimized for low conduction losses. The asymmetrical design achieves 91% system efficiency at 15 A output (12 V to 1.3 V at 500 kHz), with only 2 W total power loss under those conditions.

The 3.3×3.3-mm package occupies only 10.89 mm² — less than half the area of the 5×6-mm CSD87350Q5D — making it ideal for point-of-load (POL) converters in space-constrained applications such as notebook VRMs, embedded processor power, and industrial control systems. The exposed thermal pad (PGND) provides 2°C/W junction-to-case thermal resistance for efficient heat removal through the PCB.

The device is rated for 20-A continuous operation and 120-A pulsed current. The 30-V drain-to-source voltage supports 5-V, 12-V, and 19-V input rails. Switching frequency support up to 1.5 MHz enables very small inductors. The device pairs with TI’s TPS53819A and similar controllers for multi-phase VRM, or with any 5-V gate driver for standalone POL converters.

**Half-Bridge Configuration:** The CSD87330Q3D integrates two N-channel MOSFETs in a half-bridge: Q1 (control FET, high-side) connects VIN to SW, Q2 (sync FET, low-side) connects SW to PGND. During Q1 on-time, inductor current flows from VIN through Q1 to the output. During Q2 on-time, inductor current freewheels through Q2.

**Asymmetrical MOSFET Optimization:** Q1 is optimized for fast switching with low gate charge (Qg = 4.8 nC) and moderate RDS(on). Q2 is optimized for low conduction loss with very low RDS(on), since it conducts for a larger fraction of the cycle at low duty cycles. This asymmetry is fundamental to efficient buck converter design.

**Copper Clip Interconnect:** The internal copper clip directly connects the control FET drain to the sync FET drain, reducing loop inductance to sub-100 pH versus 0.5-2 nH for wire-bonded discrete solutions. This dramatically reduces switch-node ringing, allowing faster switching edges without exceeding voltage ratings.

**Gate Drive Interface:** The TG (top gate) and BG (bottom gate) pins connect directly to an external gate driver. The TGR pin is the high-side return (connected to SW). The FETs are optimized for 5-V gate drive with threshold voltages of 1.0 V (Q1) and 0.75 V (Q2). Maximum VGS is 8 V for both FETs.