TPS5430DAR

The TPS5430DDAR is a 3A step-down (buck) DC-DC converter manufactured by Texas Instruments, part of the SWIFT family. It features a wide input voltage range of 5.5V to 36V with an adjustable output voltage from 1.22V to 31V, set via an external resistor divider with 1.5% initial reference accuracy. The device integrates a 100 mOhm high-side N-channel MOSFET switch, achieving up to 95% efficiency.

The fixed 500 kHz switching frequency enables use of small external inductors and capacitors, minimizing solution footprint. Internal compensation simplifies design by eliminating external compensation network components. An input voltage feedforward circuit improves line regulation and transient response across the wide input range.

Key protection features include cycle-by-cycle overcurrent limiting, output overvoltage protection via a fast OVP comparator, undervoltage lockout (UVLO) that prevents operation below 5.5V input, and thermal shutdown. An active-high ENA (enable) pin with internal pull-up allows on/off control; pulling ENA below 0.5V disables the device and reduces quiescent current to 15 uA typical.

The internal slow-start circuit ramps the output voltage over 8 ms typical, limiting inrush current and preventing output overshoot during startup. A BOOT pin requires an external 0.01 uF bootstrap capacitor between BOOT and PH (phase node) to drive the high-side MOSFET gate.

The device is packaged in a thermally enhanced 8-pin SO PowerPAD (DDA) package with an exposed thermal pad for efficient heat dissipation. Operating junction temperature range is -40 to +125C. MSL-2 (260C, 1 year). Lead-free (NiPdAu finish), RoHS compliant, REACH compliant. ECCN: EAR99. Product status: Active.

The TPS5430DDAR operates as a current-mode PWM buck converter with the following subsystem architecture:

1. Power Stage: The integrated 100 mOhm N-channel MOSFET switches the input voltage to the output inductor at 500 kHz. During the on-time, current flows from VIN through the MOSFET, through the output inductor to the load, and returns through GND. During the off-time, the inductor current freewheels through the external Schottky catch diode. The 500 kHz fixed frequency is set by an internal oscillator, and the duty cycle is modulated by the feedback loop.

2. Voltage Mode Control with Feedforward: The error amplifier compares the VSENSE pin voltage (from the output resistor divider) against the 1.221V internal reference. The error signal controls the PWM comparator, which determines the MOSFET on-time. Input voltage feedforward adjusts the PWM ramp slope proportionally to VIN, maintaining constant loop gain and improving line transient response across the wide 5.5-36V input range.

3. Internal Compensation: The feedback loop is internally compensated with a Type III network, eliminating external compensation components. This simplifies design but constrains the allowable output inductor and capacitor values to maintain stability (typically 10-22 uH inductor and 100-440 uF output capacitor).

4. Bootstrap Gate Drive: The BOOT pin provides gate drive voltage for the high-side MOSFET. An external 0.01 uF capacitor between BOOT and PH is charged during the off-time when PH is near ground. During the on-time, the BOOT capacitor provides the voltage above VIN needed to drive the N-channel MOSFET gate.

5. Protection Mechanisms: Cycle-by-cycle current limiting protects the MOSFET by terminating the on-time when the peak inductor current exceeds the limit. Overvoltage protection (OVP) turns off the MOSFET when VSENSE exceeds 112.5% of the reference. UVLO holds the device in reset until VIN exceeds the start threshold. Thermal shutdown disables switching when junction temperature exceeds the threshold.

6. Enable and Slow Start: The ENA pin provides on/off control. When enabled, the internal slow-start circuit ramps the reference from 0V to 1.221V over 8 ms, limiting inrush current. The slow-start also prevents output overshoot after fault recovery.