The MAX40203AUK+T operates as an active ideal diode using an internal P-channel MOSFET with intelligent control circuitry.
Internal MOSFET and Controller: The core element is a P-channel MOSFET connected between the VDD (input) and OUT (output) pins. A P-channel MOSFET is used because it can be turned on with a gate voltage lower than the source (VDD), which is naturally available without a charge pump. The MOSFET is sized to carry 1A continuous current with minimal voltage drop. The on-resistance is designed such that at 1A forward current, the voltage drop (VDD – OUT) is approximately 90mV (SOT-23 package).
Forward-Bias Detection: An internal comparator continuously monitors the voltage difference between VDD and OUT. When VDD exceeds OUT by more than the forward turn-on threshold (approximately 10-20mV), the comparator output signals the gate driver to turn on the MOSFET. The MOSFET gate is driven to a voltage that allows the desired forward current to flow. As the load current increases, the gate drive strengthens to maintain the MOSFET in the linear region with controlled voltage drop. At low currents (1mA), the drop is only 14mV; at 1A, the drop increases to approximately 90mV due to the MOSFET on-resistance.
Reverse-Bias Blocking: When OUT exceeds VDD (reverse-bias condition), the comparator detects this within 80us and turns off the MOSFET gate drive. The MOSFET turns off, blocking reverse current flow. The reverse blocking threshold is approximately 26mV (VOUT – VDD), meaning the device turns off when the output voltage exceeds the input by 26mV. Once the MOSFET is off, the reverse leakage current is less than 10nA typical, which is far lower than a Schottky diode (typically 1-100uA at rated voltage). The device blocks voltages up to 6V in the reverse direction.
Enable Control: The EN pin provides an external control input. When EN is driven HIGH (above the enable threshold, approximately 1.0V), the ideal diode function is enabled and the device operates normally. When EN is driven LOW (below the disable threshold, approximately 0.4V), the gate driver is forced off regardless of the VDD-OUT voltage, and the MOSFET is turned off. In the disabled state, the device blocks up to 6V in both directions and draws minimal current from both VDD and EN pins.
Current Limiting: The internal current-limit circuit monitors the MOSFET current. When the forward current exceeds approximately 2A (such as during an output short circuit or a fast power-up into a large capacitive load), the gate drive is reduced to limit the current. The current limit operates in a constant-current mode, maintaining approximately 2A through the MOSFET. The resulting power dissipation (VDD x 2A) causes the junction temperature to rise.
Thermal Protection: When the junction temperature exceeds the thermal shutdown threshold (approximately 145C), the MOSFET is turned off to prevent damage. The thermal shutdown has 14C of hysteresis, meaning the device does not restart until the junction temperature drops to approximately 131C. This thermal cycling continues as long as the overcurrent condition persists, providing self-protection without requiring external intervention. The thermal protection also protects downstream circuitry by limiting the power that can be delivered into a fault.
Low Quiescent Current: The 300nA quiescent current is achieved through the use of sub-threshold CMOS design techniques in the control circuitry. The comparator, bias circuits, and gate driver are all designed to operate at nanoampere current levels. The quiescent current is relatively constant over the load current range because the control circuitry operates independently of the load current path. The low quiescent current ensures minimal battery drain in always-on applications such as backup power systems and portable devices in sleep mode.